Details, datasheet, quote on part number: PDSP16116AMCGGDR
CategoryAnalog & Mixed-Signal Processing => Analog Multipliers
Description16 X 16 Bit Complex Multiplier
CompanyMitel Networks Corporation
DatasheetDownload PDSP16116AMCGGDR datasheet
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Features, Applications

The PDSP16116 contains four 16316 array multipliers, two 32-bit adder/subtractors and all the control logic required to support Block Floating Point Arithmetic as used in FFT applications. The PDSP16116A variant will multiply two complex (16116) bit words every 50ns and can be configured to output the complete complex (32132) bit result within a single cycle. The data format is fractional two's complement. In combination with a PDSP16318A, the PDSP16116A forms a two-chip 20MHz complex multiplier accumulator with 20-bit accumulator registers and output shifters. The PDSP16116A in combination with two PDSP16318As and two PDSP1601As forms a complete 20MHz Radix 2 DIT FFT butterfly solution which fully supports block floating point arithmetic. The PDSP16116 has an extremely high throughput that is suited to recursive algorithms as all calculations are performed with a single pipeline delay (two cycle fall-through).

FEATURES I Complex Number (16116)3(16116) Multiplication I Full 32-bit Result I 20MHz Clock Rate I Block Floating Point FFT Butterfly Support I (21)3(21) Trap I Two's Complement Fractional Arithmetic I TTL Compatible I/O I Complex Conjugation I 2 Cycle Fall Through I 144-pin PGA or QFP packages APPLICATIONS I Fast Fourier Transforms I Digital Filtering I Radar and Sonar Processing I Instrumentation I Image Processing ORDERING INFORMATION

PDSP16116 MC GGDR PDSP16116A MC GGDR 10MHz MIL-883 screened 20MHz Industrial 20MHz Military 20MHz Industrial 20MHz MIL-883 screened 25MHz Industrial 315MHz Industrial

PDSP16256 PDSP16510 Complex Accumulator (16116)3(12112) Complex Multiplier Pythagoras Processor ALU and Barrel Shifter Precision Digital Modulator Programmable FIR Filter Single Chip FFT Processor

Many algorithms using complex arithmetic require conjugation of complex data stream. This operation has traditionally required an additional ALU to multiply the imaginary component by -1. The PDSP16116 eliminates this requirement by offering on-chip complex conjugation of either of the two incoming complex data words with no loss in throughput.

In multiply operations using two's complement fractional notation, the (21)3(21) operation forms an invalid result because 11 is not representable in the fractional number range. The PDSP16116 eliminates this problem by trapping the (21)3(21) operation and forcing the multiplier result to become the most positive representable number.

As with all PDSP family members the PDSP16116 has registered l/O for data and control. Data inputs have independent clock enables and data outputs have independent three state output enables. Normal mode configuration

Type Input Output Input Output Input Power

Description 16-bit input for real X data 16-bit input for imaginary X data 16-bit input for real Y data 16-bit input for imaginary Y data 16-bit output for real P data 16-bit output for imaginary P data Clock; new data is loaded on rising edge of CLK Clock, enable X-port input register Clock, enable Y-port input register Conjugate X data Conjugate Y data Rounds the real and imaginary results Mode select (BFP/Normal) Start of BFP operations (see Note 1) End of pass (See Note 1) 3 MSBs from real part of A-word (See Note 1) 3 MSBs from imaginary part of A-word (See Note 1) Word tag from A-word Word tag from B-word/shift control (See Note 2) Word tag output (See Note 1) Shift control for A-word / overflow flag (See Note 2) Shift control for accumulator result (See Note 1) Global weighting register contents (See Note 1) Selects the desired output configuration Output enables 15V Supply (See Note 3) 0V Supply (See Note 3)

NOTES 1. Used only in BFP mode 2. Performs different functions in BFP/Normal modes 3. All supply pins must be connected



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