Details, datasheet, quote on part number: PDSP1601MCGGCR
PartPDSP1601MCGGCR
CategoryLogic => Level Shifters
DescriptionAlu And Barrel Shifter
CompanyMitel Networks Corporation
DatasheetDownload PDSP1601MCGGCR datasheet
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Features, Applications

The is a high performance 16-bit arithmetic logic unit with an independent on-chip 16-bit barrel shifter. The PDSP1601A has two operating modes giving or 10MHz register-to-register transfer rates. The PDSP1601 supports Multicycle multiprecision operation. This allows a single device to operate at 20MHz for 16-bit fields, 10MHz for 32-bit fields and 5MHz for 64-bit fields. The PDSP1601 can also be cascaded to produce wider words at the 20MHz rate using the Carry Out and Carry In pins. The Barrel Shifter is also capable of extension, for example the PDSP1601 can used to select a 16-bit field from a 32-bit input in 100ns.

FEATURES

16-bit, 32 instruction 20MHz ALU 16-bit, 20MHz Logical, Arithmetic or Barrel Shifter Independent ALU and Shifter Operation 16-bit On Chip Scratchpad Registers Multiprecision Operation; e.g. 200ns 64-bit Accumulate Three Port Structure with Three Internal Feedback Paths Eliminates I/O Bottlenecks Block Floating Point Support 300mW Maximum Power Dissipation 84-pin Pin Grid Array or 84 Contact LCC Packages or 100 pin Ceramic Quad Flat Pack

APPLICATIONS

Digital Signal Processing Array Processing Graphics Database Addressing High Speed Arithmetic Processors

PDSP16318 PDSP16330 Complex Multiplier x 16 Complex Multiplier Complex Accumulator Pythagoras Processor

Further details of the Military grade part are available in a separate datasheet (DS3763)
N/C = not connected - leave open circuit All GND and VDD pin must be used

Symbol MSB MSS - B0 CEB CLK - A0 CEA MSC - SV3 Description ALU B-input multiplexer select control.1 This input is latched internally on the rising edge of CLK. Shifter Input multiplexer select control.1 This input is latched internally on the rising edge of CLK. B Port data input. Data presented to this port is latched into the input register on the rising edge of CLK. B15 is the MSB. Clock enable, B Port input register. When low the clock to this register is enabled. Common clock to all internal registered elements. change on the rising edge of CLK. All registers are loaded, and outputs

ALU A-input multiplexer select control.1 These inputs are latched internally on the rising edge of CLK. A Port data input. Data presented to this port is latched into the input register on the rising edge of CLK. A15 is the MSB. Clock enable, A Port input register. When low the clock to this register is enabled. C-Port multiplexer select control.1 This input is latched internally on the rising edge of CLK. Instruction inputs to Barrel Shifter, = MSB.1 These inputs are latched internally on the rising edge of CLK. Shift Value I/O Port. This port is used as an input when shift values are supplied from external sources, and as an output when Normalise operations are invoked. The I/O functions are determined by the - IS3 instruction inputs, and by the SVOE control. The shift value is latched internally on the rising edge of CLK. SV Output enable. When high the SV port can only operate as an input. When low the SV port can act as an input as an output, according to the - IS3 instruction. This pin should be tied hihg or low, depending upon the application. Instruction inputs to Barrel Shifter registers.1 These inputs are latched internally on the rising edge of CLK. C Port data output. Data output on this port is selected by the C output multiplexer. C15 is the MSB. Output enable. The C Port outputs are in high impedance condition when this control is high. Block Floating Point Flag from ALU, active high. Carry out from MSB of ALU. Instruction inputs to ALU registers.1 These inputs are latched internally on the rising edge of CLK. Carry in to LSB of ALU. Instruction inputs IA4 = MSB. These inputs are latched internally on the rising edge of CLK. +5V supply: Both Vcc pins must be connected. 0V supply: Both GND pins must be connected.

All instructions are executed in the cycle commencing with the rising edge of the CLK which latches the inputs.


 

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