Details, datasheet, quote on part number: PDSP1601GC1R
PartPDSP1601GC1R
CategoryDSPs (Digital Signal Processors) => Arithmetic Logic Units
TitleArithmetic Logic Units
DescriptionDescription = Alu And Barrel Shifter ;; Package Type = Flatpack ;; No. Of Pins = 100
CompanyZarlink Semiconductor
DatasheetDownload PDSP1601GC1R datasheet
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Features, Applications

The is a high performance 16-bit arithmetic logic unit with an independent on-chip 16-bit barrel shifter. The PDSP1601 supports Multicycle multiprecision operation. This allows a single device to operate at 10MHz for 16-bit-bit-fields, 5MHz for 32-bit fields and 2.5MHz for 64-bit fields. The PDSP1601 can also be cascaded to produce wider words at the 10MHz rate using the Carry Out and Carry In pins. The Barrel Shifter is capable of extension, for example the PDSP1601 can used to select a 16-bit field from a 32-bit input in 100ns.

FEATURES

16-bit, 32 instruction 10MHz ALU 16-bit, 10MHz Logical, Arithmetic or Barrel Shifter Independent ALU and Shifter Operation 16-bit On Chip Scratchpad Registers Multiprecision Operation; e.g. 200ns 64-bit Accumulate Three Port Structure with Three Internal Feedback Paths Elimates I/O Bottlenecks 300mW Maximum Power Dissipation 100-pin Ceramic Quad Flatpack Digital Signal Processing Array Processing Graphics Database Addressing High Speed Arithmetic Processors

APPLICATIONS
ORDERING INFORMATION PDSP1601/MC/GC1R (Ceramic QFP Package MIL STD 883 Class B Screening)

Symbol MSB MSS - B0 CEB CLK Pin No. (GG100 Package) Description ALU B-input multiplexer select control.1 This input is latched internally on the rising edge of CLK. Shifter Input multiplexer select control.1 This input is latched internally on the rising edge of CLK. B Port data Input. Data presented to this port is latched into the input register on the rising edge of CLK. B15 is the MSB. Clock enable, B Port input register. When low the clock to this register is enabled. Common clock to all internal registered elements. change on the rising edge of CLK. All registers are loaded, and outputs

ALU A-input multiplexer select control.1 This input are latched internally on the rising edge of CLK. A Port data Input. Data presented to this port is latched into the input register on the rising edge of CLK. B15 is the MSB. Clock enable, A Port input register. When low the clock to this register is enabled. C-Port multiplexer select control.1 This input is latched internally on the rising edge of CLK. Instruction inputs to Barrel Shifter, = MSB.1 This input is latched internally on the rising edge of CLK. Shift Value I/O Port. This port is used as an input when shift values are supplied form external sources, and as an output when Normalise operations are invoked. The I/O functions are determined by the - IS3 instruction inputs, and by the SVOE control. The shift value is latched internally on the rising edge of CLK. SV Output enable. When high the SV port can only operate as an input. When low the SV port can act as an input as an output, according to the - IS3 instruction. This pin should be tied high or low, depending upon the application. Instruction inputs to Barrel Shifter registers.1 These input are latched internally on the rising edge of CLK. C Port data output. Data output on this port is selected by the C output multiplexer. C15 is the MSB Output enable. The C Port outputs are in high impedance condition when this control is high Block Floating Point Flag from ALU, active high. Carry out from MSB of ALU Instruction inputs to ALU registsers.1 These inputs are latched interally on the rising edge of CLK. Carry in to LSB of ALU Instruction inputs IA4 = MSB. These inputs are latched internally on the rising edge of CLK. +5V supply: Both Vcc pins must be connected. 0V supply: Both GND pins must be connected.

NOTES 1. All instructions are executed in the cycle commencing with the rising edge of the CLK which latches the inputs.

SHIFTER REG FILE LEFT REG. RIGHT REG.

The PDSP1601 contains four main blocks: the ALU, the Barrel Shifter and the two Register Files. The ALU The ALU supports 32 instructions as detailed in Table 1. The inputs to the ALU are selected by the A and B MUXs. Data will fall through from the selected register through the or B input MUXs and the ALU to the ALU output register file in 100ns. The ALU instructions are latched, such that the instruction will not start executing until the rising edge of CLK latches the instruction into the device. The ALU accepts a carry in from the CI input and supplies a carry out to the CO output. Additionally, at the end of each cycle, the carry out from the ALU is loaded into an internal 1 bit register, so that it is available as an input to the ALU on the next cycle. In the manner, Multicycle, multiprecisiion operations are supported. (See MULTICYCLE CASCADE OPERATIONS). BFP Flag The ALU has a user programmable BFP flag. This flag may be programmed to become active at any one of four conditions. Two of these conditions are intended to support Block Floating Point operations, in that they provide flags indicating that the ALU result is within a factor of two or four of overflowing the 16 bit number range. For multiprecision operations the flag is only valid whilst the most significant 16 bit byte is being processed. In this manner the BFP flag may be used over any extended word width. The remaining two conditions detect either an overflow condition or a zero result. For the overflow condition to be active the ALU result must have overflowed into the 16th (sign) bit, (this flag is only valid whilst the most significant 16 bit byte is being processed). The zero condition is active if the result from the ALU is equal to zero. For multiprecision operations the zero flag must be active for all of the 16 bit bytes of an extended word. The BFP flag is programmed by executing on of the four SBFXX instructions (see Table 1). During the execution of any of these four instructions, the output of the ALU is forced to zero. Multicycle/Cascade Operation The ALU arithmetic instructions contain two or three options for each arithemtic operation. The ALU is designed to operate with two's complement arithmetic, requiring a one to be added to the LSB for all subtract operations. The instructions set includes instructions that will force a one into the LSB, e.g. AMBX1, BMAX1 (see Table 1). These instructions are used for the least significant 16 bits of any subtract operation. The user has an option of cascading multiple devices, or multicycling a single device to extend the arithmetic precision. Should the user cascade multiple devices, then the cascaded arithmetic instructions using the external CI input should be employed for all but the least significant 16 bits, e.g. MIACI, APBCI, BMACI (see Table 1). Should the user multicycle a single device, then the Multicycle Arithmetic instructions, using the internally registered CO bit should be employed for all but the least significant 16 bits, e.g. MIACO, APBCO, AMBCO, BMACO (see Table 1).


 

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