Details, datasheet, quote on part number: JDUCGCKTN
CategoryTiming Circuits => Oscillators => VCXO (Voltage Controlled Crystal Oscillators)
DescriptionFrequency Range = 1.024MHz - 180MHz ;; Output = CMOS / Pecl ;; Package (mm) = 14.0 X 9.0 ;; Features = Industry Standard J Lead SMD Low Jitter
CompanyVectron International
DatasheetDownload JDUCGCKTN datasheet


Features, Applications


Output Frequencies from 1.024 MHz to 170.000 MHz or +5.0 volt options Small x 9mm J-type Package CMOS or PECL Outputs Low phase noise and custom options 40/85 C operating temperature Tri-State output (CMOS) Enable/Disable (PECL)

Clock Smoothing Frequency Translation SONET, SDH, ATM, DSLAM, ADM

The J-type voltage controlled crystal oscillator incorporates VI's advanced VCXO performance capabilities while adhering to a package footprint compatible with the industry-common J-lead package. The J-type VCXO is a quartz stabilized square wave generator with either a CMOS output for driving CMOS/TTL loads or a PECL output. The device is packaged a 6 pin J-lead ceramic package and is hermetically sealed with a grounded conductive lid.

CMOS Output Option Electrical Performance @ 25C for the CMOS output option

Supply Voltage1, +5 volt option +3.3 volt option Supply Current Center Frequency, see ordering information Operating Temperature, see ordering info Absolute Pull Range over the operating temperature range, aging and power supply at 5V supply at 3.3V supply see ordering information for options Gain Transfer (Frequency vs. Control Voltage) Output Level High2 Output Level Low2 Output Rise/Fall Time2 Duty Cycle3, see ordering info Control Input Leakage Control Voltage Modulation Bandwidth RMS Jitter, Output=12.0-77.760 MHz RMS Jitter, Output=12.0-77.760 MHz. Band=12.0 KHz - 20 MHz Control Range Maximum Supply Voltage Storage Temperature Soldering Temp./Time

1. Power supply bypass is required and 0.1uF in parallel with a 0.01uF high frequency capacitor is recommended. 2. Figure 1 defines these parameters. Figure 2 illustrates the load used to test devices. 3. Duty cycle is defined as on-time versus period 1.4 V for TTL, and 2.5 V for CMOS (5volt supply) and 1.65 V for CMOS (3.3 volt operation)

VCXO Control Voltage. TTL logic low disables output TTL logic high, or no connect, enables output Case and electrical ground. VCXO Output TTL logic low optimizes symmetry for CMOS TTL logic high, or NC, optimizes symmetry for TTL. Power Supply Voltage 3.3V 10%)

1. Standard option. Tri-State can be connected to pin 5 and CMOS/TTL select would be on pin 2. Output is HCMOS. For frequencies >12MHz, this option optimizes symmetry for either CMOS or TTL thresholds. Ground this pin for frequencies < 12MHz.

Vectron International 267 Lowell Road, Hudson, NH 03051 Tel: 1-88-VECTRON-1 Fax: 1-888-FAX-VECTRON

Figure 1 Output Wave Form Figure 2 Output Test Conditions

Output Test Conditions (255C) for 5 volt devices. For 3.3V use 15pF cap only, no resistors needed.

Ordering Information for the CMOS output option (add frequency)4

1. Output is CMOS and symmetry is tested at TTL and CMOS thresholds. 2. Output is CMOS and symmetry is tested at CMOS threshold. This option is used for 3.3 V operation. 3. Output is CMOS and symmetry is tested at CMOS thresholds. This option is required for 3.3V, frequencies >51.840MHz. 4. Note: Not all combinations are possible.

Example: JDUGCKTN @ 77.76 MHz = 3.3 volt, VCXO@77.760, 50 ppm APR, 0/70C, 40/60% Symmetry, CMOS, Tri-State on pin 2.

Standard Frequencies, in MHz, for CMOS output option

1. Uses a PLL multiplier, jitter is 25ps rms typical vs 3ps rms typical for a HFF (High Frequency Fundemental) design. Available with 5 Vdc input only. Other frequencies available upon request.


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