Details, datasheet, quote on part number: SN74HC652DW
PartSN74HC652DW
CategorySemiconductors => Logic => Buffer/Driver/Transceiver => Registered Transceiver
Part familySN74HC652 Octal Bus Transceivers And Registers With 3-State Outputs
TitleRegistered Transceivers
DescriptionOctal Bus Transceivers And Registers With 3-State Outputs 24-SOIC -40 to 85
CompanyTexas Instruments, Inc.
StatusACTIVE
ROHSY
SampleNo
DatasheetDownload SN74HC652DW datasheet
Cross ref.Similar parts: CD74HC652M, M74HC652M1R, M74HC652M1, DV74HC652DW, 74HC652D, 74HC652D,112, 74HC652D,118, 935051190118
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Specifications 
Bits(#)8
ICC @ Nom Voltage(Max)(mA)0.08
F @ Nom Voltage(Max)(Mhz)28
Operating Temperature Range(C)-40 to 85
Technology FamilyHC
RatingCatalog
Approx. Price (US$)0.71 | 1ku
Schmitt TriggerNo
Package GroupSOIC
Output Drive (IOL/IOH)(Max)(mA)-6/6
VCC(Max)(V)6
VCC(Min)(V)2
tpd @ Nom Voltage(Max)(ns)29
Voltage(Nom)(V)6
  Mecanical Data
Pin nbPackage typeInd stdJEDEC codePackage qtyCarrierDevice markWidth (mm)Length (mm)Thick (mm)Pitch (mm)
24DWSOICR-PDSO-G25TUBEHC652 7.515.42.351.27

 

Features, Applications

Wide Operating Voltage Range 6 V High-Current 3-State Outputs Can Drive To 15 LSTTL Loads Low Power Consumption, 80-A Max ICC Typical tpd ns 6-mA Output Drive 5 V

Low Input Current 1 A Max Independent Registers and Enables for A and B Buses Multiplexed Real-Time and Stored Data True Data Paths

The 'HC652 devices consist of bus-transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. Output-enable (OEAB and OEBA) inputs are provided to control the transceiver functions. Select-control (SAB and SBA) inputs are provided to select real-time or stored-data transfer. A low input level selects real-time data, and a high input level selects stored data. Figure 1 illustrates the four fundamental bus-management functions that can be performed with these devices. ORDERING INFORMATION

TA PACKAGE PDIP to 85C SOIC DW CDIP to 125C CFP W LCCC FK Tube Tape and reel Tube ORDERABLE PART NUMBER SNJ54HC652W SNJ54HC652FK TOP-SIDE MARKING SNJ54HC652W SNJ54HC652FK

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303

Data on the or B data bus, or both, can be stored in the internal D-type flip-flops by low-to-high transitions at the appropriate clock (CLKAB or CLKBA) terminals, regardless of the select- or output-control terminals. When SAB and SBA are in the real-time transfer mode, it is possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input. When all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains at its last state. To ensure the high-impedance state during power up or power down, OEBA should be tied to VCC through a pullup resistor, and OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver.

FUNCTION TABLE INPUTS OEAB OEBA CLKAB or L CLKBA or L SAB SBA A1A8 Input Unspecified Output Input Output DATA I/O B1B8 Input Unspecified Output Input Output OPERATION OR FUNCTION Isolation Store A and B data Store A, hold B Store A in both registers Hold A, store B Store B in both registers Real-time B data to A bus Stored B data to A bus Real-time A data to B bus Stored A data to B bus Stored A data to B bus and stored B data to A bus

The data-output functions are enabled or disabled by a variety of level combinations at OEAB or OEBA. Data-input functions always are enabled; i.e., data at the bus terminals is stored on every low-to-high transition on the clock inputs. Select control = L: clocks can occur simultaneously. Select control = H: clocks must be staggered to load both registers.

BUS B 22 SBA X REAL-TIME TRANSFER BUS A TO BUS B 1 CLKAB L 23 CLKBA L 2 SAB H BUS B 22 SBA H TRANSFER STORED DATA TO A AND/OR B


 

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