|Category||Semiconductors => Logic => Flip-Flop/Latch/Register => Shift Register|
|Part family||SN74HC595 8-Bit Shift Registers With 3-State Output Registers|
|Description||8-Bit Shift Registers With 3-State Output Registers 16-SOIC -40 to 85|
|Company||Texas Instruments, Inc.|
|Datasheet||Download SN74HC595 datasheet
|Cross ref.||Similar parts: CD74HC4094M, CD74HC4094M96, CD74HC166E, CD74HC165E, CD74HC165EX, CD74HC165M, CD74HC165M96, CD74HC166EX, CD74HC166M, CD74HC166M96|
|tpd @ Nom Voltage(Max)(ns)||34|
|ICC @ Nom Voltage(Max)(mA)||0.08|
|F @ Nom Voltage(Max)(Mhz)||28|
|Operating Temperature Range(C)||-40 to 85|
|Approx. Price (US$)||0.14 | 1ku|
|Output Drive (IOL/IOH)(Max)(mA)||7.8/-7.8|
|Pin nb||Package type||Ind std||JEDEC code||Package qty||Carrier||Device mark||Width (mm)||Length (mm)||Thick (mm)||Pitch (mm)|
|• Hardware Design Considerations for a Wireless LED based Display Design
Scoreboards have different purposes with various features. Scoreboards are typically used for displaying scores of a game played between two teams. These games can be a timed or an untimed event. The application described in this application report creates | Doc
|BOOSTXL-ULN2003: Dual Stepper Motor Driver BoosterPack featuring ULN2003 and CSD17571Q2 NexFETÂ™|
D 8-Bit Serial-In, Parallel-Out Shift D Wide Operating Voltage Range V D High-Current 3-State Outputs Can Drive Up
To 15 LSTTL Loads Low Power Consumption, 80-µA Max ICC Typical tpd ns ±6-mA Output Drive 5 V Low Input Current 1 µA Max Shift Register Has Direct Clear
The 'HC595 devices contain an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and serial outputs for cascading. When the output-enable (OE) input is high, the outputs are in the high-impedance state. Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both clocks are connected together, the shift register always is one clock pulse ahead of the storage register. ORDERING INFORMATION
TA PDIP N SOIC to 85°C SOIC DW SOP NS SSOP DB CDIP to 125°C CFP W LCCC FK PACKAGE Tube Tape and reel Tube Tape and reel Tape and reel Tape and reel Tube ORDERABLE PART NUMBER SNJ54HC595FK HC595
SNJ54HC595FK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
On products compliant to MILPRF38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
FUNCTION TABLE INPUTS SER SRCLK SRCLR RCLK OE FUNCTION Outputs QAQH are disabled. Outputs QAQH are enabled. Shift register is cleared. First stage of the shift register goes low. Other stages store the data of previous stage, respectively. First stage of the shift register goes high. Other stages store the data of previous stage, respectively. Shift-register state is not changed. Shift-register data is stored in the storage register. Storage-register state is not changed.
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