|Category||Semiconductors => Logic => Flip-Flop/Latch/Register => D-Type Flip-Flop|
|Part family||SN74HC574 Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs|
|Description||Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs 20-SSOP -40 to 85|
|Company||Texas Instruments, Inc.|
|Datasheet||Download SN74HC574 datasheet
|Cross ref.||Similar parts: SN74LS366AJD, SN74LS366AJDS, SN74LS366AJS, SN74LS366AN, SN74LS366AND, SN74LS366ANDS, SN74LS366ANS, SN74LS368AD, SN74LS368ADR2, SN74LS368AJD|
|ICC @ Nom Voltage(Max)(mA)||0.08|
|F @ Nom Voltage(Max)(Mhz)||28|
|Operating Temperature Range(C)||-40 to 85|
|tpd @ Nom Voltage(Max)(ns)||38|
|Approx. Price (US$)||0.12 | 1ku|
|Output Drive (IOL/IOH)(Max)(mA)||7.8/-7.8|
|Pin nb||Package type||Ind std||JEDEC code||Package qty||Carrier||Device mark||Width (mm)||Length (mm)||Thick (mm)||Pitch (mm)|
|SN54HC574, SN74HC574 OCTAL EDGETRIGGERED DTYPE FLIPFLOPS WITH 3STATE OUTPUTS
D Wide Operating Voltage Range V D High-Current 3-State Noninverting Outputs
Drive Bus Lines Directly To 15 LSTTL Loads Low Power Consumption, 80-µA Max ICC Typical tpd ns ±6-mA Output Drive 5 V Low Input Current 1 µA Max Bus-Structured Pinout
These octal edge-triggered D-type flip-flops feature 3-state outputs designed specifically for bus driving. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight flip-flops enter data on the low-to-high transition of the clock (CLK) input. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.
OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. ORDERING INFORMATION
TA PDIP N SOIC to 85°C SSOP DB SOP NS TSSOP PW CDIP to 125°C CFP W LCCC FK PACKAGE Tube Tape and reel Tape and reel Tape and reel Tape and reel Tube ORDERABLE PART NUMBER SNJ54HC574J SNJ54HC574W TOP-SIDE MARKING SN74HC574N
SNJ54HC574FK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
On products compliant to MILPRF38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.FUNCTION TABLE (each flip-flop) INPUTS OE CLK H or OUTPUT Q0 Z
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC. 7 V Input clamp current, IIK (VI VI > VCC) (see Note ±20 mA Output clamp current, IOK (VO VO > VCC) (see Note ±20 mA Continuous output current, IO (VO 0 to VCC). ±35 mA Continuous current through VCC or GND. ±70 mA Package thermal impedance, JA (see Note 2): DB package. 70°C/W DW package. 58°C/W N package. 69°C/W NS package. 60°C/W PW package. 83°C/W Storage temperature range, Tstg. to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7.
SN54HC574 MIN VCC VIH Supply voltage VCC 2 V VCC 4.5 V VCC 6 V VCC 2 V VIL VI VO t/v Low-level Low level in input ut voltage Input voltage Output voltage VCC 2 V VCC 4.5 V VCC 6 V VCC 4.5 V VCC 6 V VCC NOM 5 MAX 6 SN74HC574 MIN VCC 400 ns NOM 5 MAX 6 UNIT V
TA Operating free-air temperature °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
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