Details, datasheet, quote on part number: SN74HC573APWR
PartSN74HC573APWR
CategorySemiconductors => Logic => Flip-Flop/Latch/Register => D-Type Latch
Part familySN74HC573A Octal Transparent D-Type Latches With 3-State Outputs
TitleD-Type (3-State) Latches
DescriptionOctal Transparent D-Type Latches With 3-State Outputs 20-TSSOP -40 to 85
CompanyTexas Instruments, Inc.
StatusACTIVE
ROHSY
SampleNo
DatasheetDownload SN74HC573APWR datasheet
Cross ref.Similar parts: 74HC573PW, MC74HC573ADT, MC74HC573ADTEL, MC74HC573ADTELG, MC74HC573ADTG, MC74HC573ADTR2, MC74HC573ADTR2G, HD74HC573T, HD74HC573T-EL, HD74HC573TELL
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Specifications 
3-State OutputYes
Bits(#)8
ICC @ Nom Voltage(Max)(mA)0.08
F @ Nom Voltage(Max)(Mhz)28
Operating Temperature Range(C)-40 to 85
Technology FamilyHC
RatingCatalog
Schmitt TriggerNo
tpd @ Nom Voltage(Max)(ns)38
VCC(Max)(V)6
Package GroupPDIP,SOIC,SSOP,TSSOP
Approx. Price (US$)0.14 | 1ku
VCC(Min)(V)2
Voltage(Nom)(V)6
Output Drive (IOL/IOH)(Max)(mA)7.8/-7.8
  Mecanical Data
Pin nbPackage typeInd stdJEDEC codePackage qtyCarrierDevice markWidth (mm)Length (mm)Thick (mm)Pitch (mm)
20PWTSSOPR-PDSO-G2000LARGE T&RHC573A 4.46.51.65

 

Features, Applications
SN54HC573A, SN74HC573A OCTAL TRANSPARENT DTYPE LATCHES WITH 3STATE OUTPUTS
D Wide Operating Voltage Range V D High-Current 3-State Outputs Drive Bus
Typical tpd ns 6-mA Output Drive 5 V Low Input Current 1 A Max Bus-Structured Pinout

These octal transparent D-type latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. While the latch-enable (LE) input is high, the Q outputs respond to the data (D) inputs. When LE is low, the outputs are latched to retain the data that was set up. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. ORDERING INFORMATION

TA PDIP - N SOIC to 85C SSOP - DB TSSOP - PW CDIP to 125C CFP - W LCCC - FK PACKAGE Tube of 25 Tube of 40 Reel of 2500 Reel of 2000 Reel of 2000 Reel of 250 Tube of 25 Tube of 150 Tube of 55 ORDERABLE PART NUMBER SNJ54HC573AW SNJ54HC573AFK

SNJ54HC573AFK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

On products compliant to MILPRF38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

FUNCTION TABLE (each latch) INPUTS OE LE OUTPUT Q0 Z
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, VCC. 7 V Input clamp current, IIK (VI VI > VCC) (see Note 20 mA Output clamp current, IOK (VO VO > VCC) (see Note 20 mA Continuous output current, IO (VO 0 to VCC). 35 mA Continuous current through VCC or GND. 70 mA Package thermal impedance, JA (see Note 2): DB package. 70C/W DW package. 58C/W N package. 69C/W PW package. 83C/W Storage temperature range, Tstg. to 150C

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7.

SN54HC573A MIN VCC VIH Supply voltage VCC 2 V VCC 4.5 V VCC 6 V VCC 2 V VIL VO tt Low-level input voltage Input voltage Output voltage VCC 2 V VCC 4.5 V VCC 6 V VCC 4.5 V VCC 6 V VCC NOM 5 MAX 6 SN74HC573A MIN VCC 400 ns NOM 5 MAX 6 UNIT V

TA Operating free-air temperature C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)


 

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SN74HC573ADW
SN74HC573ADWR
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