Details, datasheet, quote on part number: SN74HC563DWR
PartSN74HC563DWR
CategorySemiconductors => Logic => Flip-Flop/Latch/Register => D-Type Latch
Part familySN74HC563 Octal Transparent D-Type Latches With 3-State Outputs
TitleD-Type (3-State) Latches
DescriptionOctal Transparent D-Type Latches With 3-State Outputs 20-SOIC -40 to 85
CompanyTexas Instruments, Inc.
StatusACTIVE
ROHSY
SampleNo
DatasheetDownload SN74HC563DWR datasheet
Cross ref.Similar parts: M74HC563RM13TR
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Specifications 
3-State OutputYes
Bits(#)8
ICC @ Nom Voltage(Max)(mA)0.08
F @ Nom Voltage(Max)(Mhz)28
Operating Temperature Range(C)-40 to 85
Technology FamilyHC
RatingCatalog
Schmitt TriggerNo
Package GroupPDIP,SO,SOIC
Approx. Price (US$)0.41 | 1ku
VCC(Max)(V)6
VCC(Min)(V)2
tpd @ Nom Voltage(Max)(ns)37
Voltage(Nom)(V)6
Output Drive (IOL/IOH)(Max)(mA)7.8/-7.8
  Mecanical Data
Pin nbPackage typeInd stdJEDEC codePackage qtyCarrierDevice markWidth (mm)Length (mm)Thick (mm)Pitch (mm)
20DWSOICR-PDSO-G2000LARGE T&RHC563 7.512.82.351.27

 

Features, Applications
SN54HC563, SN74HC563 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

Wide Operating Voltage Range 6 V High-Current 3-State Outputs Drive Bus Lines Directly To 15 LSTTL Loads Low Power Consumption, 80-A Max ICC

Typical tpd ns 6-mA Output Drive 5 V Low Input Current 1 A Max Bus-Structured Pinout

These 8-bit transparent D-type latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. While the latch-enable (LE) input is high, the Q outputs follow the complements of the data (D) inputs. When LE is taken low, the outputs are latched at the inverses of the levels set up at the D inputs. A buffered output-enable (OE) input places the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased high logic level provide the capability to drive bus lines without interface or pullup components. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. OE does not affect internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. ORDERING INFORMATION

TA PDIP to 85C SOIC DW CDIP to 125C CFP W LCCC FK PACKAGE Tube Tape and reel Tube ORDERABLE PART NUMBER SNJ54HC563W SNJ54HC563FK

SNJ54HC563FK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303

FUNCTION TABLE (each latch) INPUTS OE LE OUTPUT Q0 Z
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, VCC. 7 V Input clamp current, IIK (VI VI > VCC) (see Note 20 mA Output clamp current, IOK (VO VO > VCC) (see Note 20 mA Continuous output current, IO (VO 0 to VCC). 35 mA Continuous current through VCC or GND. 70 mA Package thermal impedance, JA (see Note 2): DW package. 58C/W N package. 69C/W Storage temperature range, Tstg. to 150C

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7.

SN54HC563 MIN VCC VIH Supply voltage High-level input voltage VCC 2 V VCC 4.5 V VCC 6 V VCC 2 V VIL VO tt Low-level input voltage Input voltage Output voltage Input transition (rise and fall) time VCC 2 V VCC 4.5 V VCC 4.5 V VCC 6 V VCC NOM 5 MAX 6 SN74HC563 MIN VCC 500 ns NOM 5 MAX 6 UNIT V

VCC 400 TA Operating free-air temperature C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.


 

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