Details, datasheet, quote on part number: SN54ALS259FK
PartSN54ALS259FK
CategoryLogic => Latches
Description8-bit Addressable Latches
CompanyTexas Instruments, Inc.
DatasheetDownload SN54ALS259FK datasheet
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Features, Applications

8-Bit Parallel-Out Storage Register Performs Serial-to-Parallel Conversion With Storage Asynchronous Parallel Clear Active-High Decoder Enable/Disable Input Simplifies Expansion Expandable for n-Bit Applications Four Distinct Functional Modes Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs

description

These 8-bit addressable latches are designed for general-purpose storage applications in digital systems. Specific uses include working registers, serial-holding registers, and active-high decoders or demultiplexers. They are multifunctional devices capable of storing single-line data in eight addressable latches and being a 1-of-8 decoder or demultiplexer with active-high outputs.

Four distinct modes of operation are selectable by controlling the clear (CLR) and enable (G) inputs as shown in the function table. In the No internal connection addressable-latch mode, data at the data-in terminal is written into the addressed latch. The addressed latch follows the data input with all unaddressed latches remaining in their previous states. In the memory mode, all latches remain in their previous states and are unaffected by the data or address inputs. To eliminate the possibility of entering erroneous data in the latches, G should be held high (inactive) while the address lines are changing. In the 1-of-8 decoding or demultiplexing mode, the addressed output follows the level of the D input with all other outputs low. In the clear mode, all outputs are low and unaffected by the address and data inputs. The SN54ALS259 is characterized for operation over the full military temperature range to 125C. The SN74ALS259 is characterized for operation from to 70C. Function Tables

FUNCTION INPUTS CLR OUTPUT OF ADDRESSED LATCH D QiO D L EACH OTHER OUTPUT QiO L FUNCTION Addressable latch Memory 8-line demultiplexer Clear

D = the level at the data input. QiO = the level 7 as appropriate) before the indicated steady-state input conditions were established.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

LATCH SELECTION SELECT INPUTS S1 S0 LATCH ADDRESSED

G D CLR 10, 7R This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, and N packages.



 

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