Details, datasheet, quote on part number: M95128-BN6
PartM95128-BN6
CategoryMemory => ROM => EEPROM => Serial => SPI
TitleSPI
Description128KBIT Serial Spi Bus EePROM With High Speed Clock
CompanyST Microelectronics, Inc.
DatasheetDownload M95128-BN6 datasheet
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Features, Applications
128Kbit Serial SPI Bus EEPROM With High Speed Clock
FEATURES SUMMARY s Compatible with SPI Bus Serial Interface (Positive Clock SPI Modes)

High speed ­ 5MHz Clock Rate, 10ms Write Time (current product: identified by process identification letter ­ 10MHz Clock Rate, 5ms Write Time. (This product is under development. For more information please contact your nearest ST sales office) Details of how to find the process identification letter are given on page 35).

Status Register Hardware Protection of the Status Register BYTE and PAGE WRITE (up to 64 Bytes) Self-Timed Programming Cycle Adjustable Size Read-Only EEPROM Area Enhanced ESD Protection More than 100,000 Erase/Write Cycles More than 40 Year Data Retention

SUMMARY DESCRIPTION These electrically erasable programmable memory (EEPROM) devices are accessed by a high speed SPI-compatible bus. The memory array is organized x 8 bit. The device is accessed by a simple serial interface that is SPI-compatible. The bus signals are C, D and Q, as shown in Table 1 and Figure 2. The device is selected when Chip Select (S) is taken Low. Communications with the device can be interrupted using Hold (HOLD). Figure 2. Logic Diagram

Note: 1. See page 31 (onwards) for package dimensions, and how to identify pin-1.
Note: 1. See page 31 (onwards) for package dimensions, and how to identify NC = Not Connected

D Q Serial Clock Serial Data Input Serial Data Output Chip Select Write Protect Hold Supply Voltage Ground

SIGNAL DESCRIPTION During all operations, V CC must be held stable and within the specified valid range: VCC(min) to VCC(max). All of the input and output signals must be held High or Low (according to voltages of VIH, VOH, VIL or VOL, as specified in Tables to 18). These signals are described next. Serial Data Output (Q). This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C). Serial Data Input (D). This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be written. Values are latched on the rising edge of Serial Clock (C). Serial Clock (C). This input signal provides the timing of the serial interface. Instructions, addresses, or data present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on Serial Data Output (Q) changes after the falling edge of Serial Clock (C). Chip Select (S). When this input signal is High, the device is deselected and Serial Data Output (Q) is at high impedance. Unless an internal Write cycle is in progress, the device will be in the Standby mode. Driving Chip Select (S) Low enables the device, placing it in the active power mode. After Power-up, a falling edge on Chip Select (S) is required prior to the start of any instruction. Hold (HOLD). The Hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device.

During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data Input (D) and Serial Clock (C) are Don't Care. To start the Hold condition, the device must be selected, with Chip Select (S) driven Low. Write Protect (W). The main purpose of this input signal is to freeze the size of the area of memory that is protected against Write instructions (as specified by the values in the BP1 and BP0 bits of the Status Register). This pin must be driven either High or Low, and must be stable during all write operations.

CONNECTING TO THE SPI BUS These devices are fully compatible with the SPI protocol. All instructions, addresses and input data bytes are shifted in to the device, most significant bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C) after Chip Select (S) goes Low. All output data bytes are shifted out of the device, most significant bit first. The Serial Data Output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction (such as the Read from Memory Array and Read Status Register instructions) have been clocked into the device. Figure 5 shows three devices, connected to an MCU, on a SPI bus. Only one device is selected at a time, so only one device drives the Serial Data Output (Q) line at a time, all the others being high impedance.


 

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