|Category||Logic => Bus Exchangers|
|Description||256/128 Kbit Serial Spi Bus EePROM With High Speed Clock|
|Company||ST Microelectronics, Inc.|
|Datasheet||Download M95128-BN1T datasheet
|256/128 Kbit Serial SPI Bus EEPROM With High Speed Clock
SPI Bus Compatible Serial Interface Supports Positive Clock SPI Modes 5 MHz Clock Rate (maximum) Single Supply Voltage: to 5.5V for to 3.6V for to 5.5V for to 3.6V for M95xxx-R
Status Register Hardware and Software Protection of the Status Register BYTE and PAGE WRITE (up to 64 Bytes) Self-Timed Programming Cycle Resizeable Read-Only EEPROM Area Enhanced ESD Protection 100,000 Erase/Write Cycles (minimum) 40 Year Data Retention (minimum)
DESCRIPTION These SPI-compatible electrically erasable programmable memory (EEPROM) devices are organized x 8 bits (M95256) and x 8 bits (M95128), and operate down 2.7 V (for theD Q Serial Clock Serial Data Input Serial Data Output
Write Protect Hold Supply Voltage Ground
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Figure 2B. SO Connections -V version), 2.5 V (for the -W version), and down 1.8 V (for the -R version of each device). The M95256 and M95128 are available in Plastic Dual-in-Line, Plastic Small Outline and Thin Shrink Small Outline packages. Each memory device is accessed by a simple serial interface that is SPI bus compatible. The bus signals are C, D and Q, as shown in Table 1 and Figure 3. The device is selected when the chip select input (S) is held low. Communications with the chip can be interrupted using the hold input (HOLD).
Symbol TA TSTG TLEAD VO VI VCC VESD Parameter Ambient Operating Temperature Storage Temperature Lead Temperature during Soldering Output Voltage Range Input Voltage Range Supply Voltage Range Electrostatic Discharge Voltage (Human Body model) PSDIP8: 10 sec SO8: 40 sec TSSOP14: t.b.c. Value 260 215 t.b.c. 6.5 4000 Unit °C
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents. 3015.7 (100 pF, 1500 )SPI Interface with SDO (CPOL, CPHA) = SDI ('1', '1') SCK Master ST9, ST10, Others)
SIGNAL DESCRIPTION Serial Output (Q) The output pin is used to transfer data serially out of the Memory. Data is shifted out on the falling edge of the serial clock. Serial Input (D) The input pin is used to transfer data serially into the device. Instructions, addresses, and the data to be written, are each received this way. Input is latched on the rising edge of the serial clock. Serial Clock (C) The serial clock provides the timing for the serial interface (as shown in Figure 4). Instructions, addresses, or data are latched, from the input pin, on the rising edge of the clock input. The output data on the Q pin changes state after the falling edge of the clock input. Chip Select (S) When S is high, the memory device is deselected, and the Q output pin is held in its high impedance state. Unless an internal write operation is underway, the memory device is placed in its stand-by power mode. After power-on, a high-to-low transition S is required prior to the start of any operation. Write Protect (W) The protection features of the memory device are summarized in Table 3. The hardware write protection, controlled by the W pin, restricts write access to the Status Register
(though not to the WIP and WEL bits, which are set or reset by the device internal logic). Bit 7 of the status register (as shown in Table 5) is the Status Register Write Disable bit (SRWD). When this is set to 0 (its initial delivery state) it is possible to write to the status register if the WEL bit (Write Enable Latch) has been set by the WREN instruction (irrespective of the level being applied to the W input). When bit 7 (SRWD) of the status register is set to 1, the ability to write to the status register depends on the logic level being presented at pin If W pin is high, it is possible to write to the status register, after having set the WEL bit using the WREN instruction (Write Enable Latch). If W pin is low, any attempt to modify the status register is ignored by the device, even if the WEL bit has been set. As a consequence, all the data bytes in the EEPROM area, protected by the BPn bits of the status register, are also hardware protected against data corruption, and appear as a Read Only EEPROM area for the microcontroller. This mode is called the Hardware Protected Mode (HPM). It is possible to enter the Hardware Protected Mode (HPM) either by setting the SRWD bit after pulling low the W pin, or by pulling low the W pin after setting the SRWD bit. The only way to abort the Hardware Protected Mode, once entered, is to pull high the W pin. If W pin is permanently tied to the high level, the Hardware Protected Mode is never activated, and
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