Details, datasheet, quote on part number: M95080-W5
PartM95080-W5
CategoryMemory => ROM => EEPROM => Serial => SPI
TitleSPI
Description16KBIT And 8KBIT Serial Spi Bus EePROM With High Speed Clock
CompanyST Microelectronics, Inc.
DatasheetDownload M95080-W5 datasheet
  

 

Features, Applications
16Kbit and 8Kbit Serial SPI Bus EEPROM With High Speed Clock
FEATURES SUMMARY s Compatible with SPI Bus Serial Interface (Positive Clock SPI Modes)

High speed 5MHz Clock Rate, 10ms Write Time (current product: identified by process identification letter 10MHz Clock Rate, 5ms Write Time (new product: identified by process identification letter W) Details of how to find the process identification letter are given on page 33).

Status Register Hardware Protection of the Status Register BYTE and PAGE WRITE (up to 32 Bytes) Self-Timed Programming Cycle Adjustable Size Read-Only EEPROM Area Enhanced ESD Protection More than 1,000,000 Erase/Write Cycles More than 40 Year Data Retention

SUMMARY DESCRIPTION These electrically erasable programmable memory (EEPROM) devices are accessed by a high speed SPI-compatible bus. The memory array is organized x 8 bit (M95160), and x 8 bit (M95080). The device is accessed by a simple serial interface that is SPI-compatible. The bus signals are C, D and Q, as shown in Table 1 and Figure 2. The device is selected when Chip Select (S) is taken Low. Communications with the device can be interrupted using Hold (HOLD). Figure 2. Logic Diagram

Note: 1. See page 29 (onwards) for package dimensions, and how to identify pin-1.

D Q Serial Clock Serial Data Input Serial Data Output Chip Select Write Protect Hold Supply Voltage Ground

SIGNAL DESCRIPTION During all operations, V CC must be held stable and within the specified valid range: VCC(min) to VCC(max). All of the input and output signals must be held High or Low (according to voltages of VIH, VOH, VIL or VOL, as specified in Tables to 17). These signals are described next. Serial Data Output (Q). This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C). Serial Data Input (D). This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be written. Values are latched on the rising edge of Serial Clock (C). Serial Clock (C). This input signal provides the timing of the serial interface. Instructions, addresses, or data present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on Serial Data Output (Q) changes after the falling edge of Serial Clock (C). Chip Select (S). When this input signal is High, the device is deselected and Serial Data Output (Q) is at high impedance. Unless an internal Write cycle is in progress, the device will be in the Standby mode. Driving Chip Select (S) Low enables the device, placing it in the active power mode. After Power-up, a falling edge on Chip Select (S) is required prior to the start of any instruction. Hold (HOLD). The Hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device.

During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data Input (D) and Serial Clock (C) are Don't Care. To start the Hold condition, the device must be selected, with Chip Select (S) driven Low. Write Protect (W). The main purpose of this input signal is to freeze the size of the area of memory that is protected against Write instructions (as specified by the values in the BP1 and BP0 bits of the Status Register). This pin must be driven either High or Low, and must be stable during all write operations.

CONNECTING TO THE SPI BUS These devices are fully compatible with the SPI protocol. All instructions, addresses and input data bytes are shifted in to the device, most significant bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C) after Chip Select (S) goes Low. All output data bytes are shifted out of the device, most significant bit first. The Serial Data Output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction (such as the Read from Memory Array and Read Status Register instructions) have been clocked into the device. Figure 5 shows three devices, connected to an MCU, on a SPI bus. Only one device is selected at a time, so only one device drives the Serial Data Output (Q) line at a time, all the others being high impedance.


 

Related products with the same datasheet
M95080-3
M95080-5
M95080-6
M95080-BN3
M95080-BN6
M95080-MN3
M95080-MN3T
M95080-MN6
M95080-MN6T
M95080-R
M95080-R5
M95080-RBN5
Some Part number from the same manufacture ST Microelectronics, Inc.
M95080-W6 16KBIT And 8KBIT Serial Spi Bus EePROM With High Speed Clock
M95080-WBN1T 64/32/16/8 Kbit Serial Spi Bus EePROM With High Speed Clock
M95080-WBN6 16KBIT And 8KBIT Serial Spi Bus EePROM With High Speed Clock
M95080-WBN6T 64/32/16/8 Kbit Serial Spi Bus EePROM With High Speed Clock
M95080-WDW6T 16KBIT And 8KBIT Serial Spi Bus EePROM With High Speed Clock
M95080-WMN1T 64/32/16/8 Kbit Serial Spi Bus EePROM With High Speed Clock
M95080-WMN3 16KBIT And 8KBIT Serial Spi Bus EePROM With High Speed Clock
M95080-WMN3T 64/32/16/8 Kbit Serial Spi Bus EePROM With High Speed Clock
M95080-WMN3T/W 16KBIT And 8KBIT Serial Spi Bus EePROM With High Speed Clock
M95080-WMN5T 64/32/16/8 Kbit Serial Spi Bus EePROM With High Speed Clock
M95080-WMN6 16KBIT And 8KBIT Serial Spi Bus EePROM With High Speed Clock
M95080-WMN6T 64/32/16/8 Kbit Serial Spi Bus EePROM With High Speed Clock
M95080-WMN6TP 16KBIT And 8KBIT Serial Spi Bus EePROM With High Speed Clock
M95080BN 64/32/16/8 Kbit Serial Spi Bus EePROM With High Speed Clock
M95128 128KBIT Serial Spi Bus EePROM With High Speed Clock
M95128-BN1T 256/128 Kbit Serial Spi Bus EePROM With High Speed Clock
M95128-BN6 128KBIT Serial Spi Bus EePROM With High Speed Clock
M95128-BN6T 256/128 Kbit Serial Spi Bus EePROM With High Speed Clock
M95128-DL6T 128KBIT Serial Spi Bus EePROM With High Speed Clock
M95128-MN1T 256/128 Kbit Serial Spi Bus EePROM With High Speed Clock
M95128-MN6 128KBIT Serial Spi Bus EePROM With High Speed Clock

L4931CDT60 : 1.2V, Low Drop Regulator

M29W640DB70N6F : 64 Mbit 8mb x8 or 4mb X16, Boot Block 3v Supply Flash Memory

PSD4135F2-C-20B81 : Flash In-system-programmable Peripherals For 16-bit MCUs

PSD913F3-A-70B81 : Flash In-system Programmable Isp Peripherals For 8-bit MCUs

TSH31C : 280 MHZ Bandwidth MOS Input Single Op-amps

M93C76-BN3G/S : 16kbit, 8kbit, 4kbit, 2kbit and 1kbit (8-bit or 16-bit Wide) Microwire Serial Access Eeprom

VN750_04 : HIGH SIDE Driver

PSD813F2V-90J : Flash In-system Programmable ISP Peripherals For 8-bit MCUs

VN771K-E : Pmic - Mosfet, Bridge Driver - Internal Switch Integrated Circuit (ics) Surface Mount Tube 9A 5.5 V ~ 36 V; IC SSR QUAD FOR H BRIDGE 28SOIC Specifications: Package / Case: 28-SOIC (0.295", 7.50mm Width) ; Mounting Type: Surface Mount ; Type: H Bridge ; Voltage - Supply: 5.5 V ~ 36 V ; On-State Resistance: 60 mOhm ; Current - Output / Channel: 9A ; Current - Peak Output: - ; Packaging: Tube ; Input Type: Non-Inverting ; Number of Outputs

ST7232AJ1B1/XXX : 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP42 Specifications: Life Cycle Stage: ACTIVE ; Clock Speed: 16 MHz ; ROM Type: MROM ; Supply Voltage: 3.8 to 5.5 volts ; I/O Ports: 32 ; Package Type: SDIP, Other, 0.600 INCH, PLASTIC, SDIP-42 ; Operating Range: Commercial ; Pin Count: 42 ; Operating Temperature: 0 to 70 C (32 to 158 F) ; Features: PWM

 
0-C     D-L     M-R     S-Z