Details, datasheet, quote on part number: M95010-WMN3T
PartM95010-WMN3T
CategoryLogic => Bus Exchangers
Description4kbit, 2kbit And 1kbit Serial Spi Bus EePROM With High Speed Clock
CompanyST Microelectronics, Inc.
DatasheetDownload M95010-WMN3T datasheet
  

 

Features, Applications
4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock
FEATURES SUMMARY s Compatible with SPI Bus Serial Interface (Positive Clock SPI Modes)

5 MHz Clock Rate (maximum) Status Register BYTE and PAGE WRITE (up to 16 Bytes) Self-Timed Programming Cycle Adjustable Size Read-Only EEPROM Area Enhanced ESD Protection More than 1,000,000 Erase/Write Cycles More than 40 Year Data Retention

SUMMARY DESCRIPTION The a 4 Kbit x 8) electrically erasable programmable memory (EEPROM), accessed by a high speed SPI-compatible bus. The other members of the family (M95020, M95010) are identical, though proportionally smaller (2 and 1 Kbit, respectively). Each device is accessed by a simple serial interface that is SPI-compatible. The bus signals are C, D and Q, as shown in Table 1 and Figure 2. The device is selected when Chip Select (S) is taken Low. Communications with the device can be interrupted using Hold (HOLD). WRITE instructions are disabled by Write Protect (W). Figure 2. Logic Diagram

Note: 1. See page 28 (onwards) for package dimensions, and how to identify pin-1.

D Q Serial Clock Serial Data Input Serial Data Output Chip Select Write Protect Hold Supply Voltage Ground

SIGNAL DESCRIPTION VCC must be held within the specified range: VCC(min) to VCC(max). All of the input and output signals can be held High or Low (according to voltages of VIH, VOH, VIL or VOL, as specified in Tables to 16). These signals are described next. Serial Data Output (Q) This output signal is used to transfer data serially out of the device. Data bytes are shifted out on the falling edge of the Serial Clock (C). Serial Data Input (D) This input signal is used to transfer data serially into the device. Instructions, addresses, and input data bytes are shifted in on the rising edge of the Serial Clock (C). Serial Clock (C) This input signal provides the timing for the serial interface.

Chip Select (S) When this input signal is High, the device is deselected, and the Serial Data Output (Q) is high impedance. Hold (HOLD) This input signal is used to pause temporarily any serial communications with the device, without losing bits that have already been passed on the serial bus. Write Protect (W) This input signal is used to control whether the memory is write protected. When W is held Low, writes to the memory are disabled, but other operations remain enabled. No action on this signal, or on the Write Enable Latch (WEL) bit, can interrupt a Write cycle that has already started.


 

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