|Category||Memory => SRAM|
|Description||64 Kbit 8kb x8 Timekeeper SRAM With Address/data Multiplexed|
|Company||ST Microelectronics, Inc.|
|Datasheet||Download M48T559YMH datasheet
|64 Kbit (8Kb x8) TIMEKEEPER® SRAM with ADDRESS/DATA MULTIPLEXED
SOFTWARE and HARDWARE RESET for WATCHDOG TIMER REGISTER COMPATIBLE with M48T59 TIMEKEEPER SRAM ADDRESS/DATA MULTIPLEXED I/O PINS WATCHDOG TIMER - MONITORS OUT of CONTROL PROCESSOR or HUNG BUS ALARM with WAKE-UP in BATTERY MODE INTEGRATED ULTRA LOW POWER SRAM, REAL TIME CLOCK, POWER-FAIL CONTROL CIRCUIT and BATTERY FREQUENCY TEST OUTPUT for REAL TIME CLOCK AUTOMATIC POWER-FAIL CHIP DESELECT and WRITE PROTECTION WRITE PROTECT VOLTAGE (VPFD = Power-fail Deselect Voltage): M48T559Y: 4.2V VPFD 4.5V PACKAGING INCLUDES a 28-LEAD SOIC and SNAPHAT® TOP (to be Ordered Separately) SOIC PACKAGE PROVIDES DIRECT CONNECTION for a SNAPHAT TOP CONTAINS the BATTERY and CRYSTAL MICROPROCESSOR POWER-ON RESET (Valid even during battery back-up mode) PROGRAMMABLE ALARM OUTPUT ACTIVE in the BATTERY BACK-UP MODE
DESCRIPTION The M48T559Y TIMEKEEPER ® RAM x 8 non-volatile static RAM and real time clock. The monolithic chip is available in the SNAPHAT package to provide a highly integrated battery backedup memory and real time clock solution. The 28 pin 330mil SOIC provides sockets with gold plated contacts at both ends for direct connection to a separate SNAPHAT housing containing the battery and crystal. The unique design allows the SNAPHAT battery package to be mounted on top of the SOIC package after the completion of the surface mount process.Figure 2. SOIC Connections Table 1. Signal Names
AD0-AD7 AS0-AS1 Address/Data Address Strobes Write Enable Read Enable Chip Enable Watchdog Input Reset Input Power Fail Reset Output (Open Drain) Interrupt / Frequency Test Output (Open Drain) Supply Voltage Ground Not Connected Internally Don't Use must be connected to VCC or VSS
Symbol TA TSTG VIO VCC IO PD Parameter Ambient Operating Temperature Storage Temperature (VCC Off, Oscillator Off) Input or Output Voltages Supply Voltage Output Current Power Dissipation Value 20 1 Unit mA W
Note: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect reliability.
CAUTION: Negative undershoots below 0.3V are not allowed on any pin while in the Battery Back-up mode. CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
Insertion of the SNAPHAT housing after reflow prevents potential battery and crystal damage due to the high temperatures required for device surface-mounting. The SNAPHAT housing is keyed to prevent reverse insertion. The SOIC and battery/crystal packages are shipped separately in plastic anti-static tubes or in Tape & Reel form. For the 28 lead SOIC, the battery/crystal package (i.e. SNAPHAT) part number is "M4T28-BR12SH1". Caution: Do not place the SNAPHAT battery/crystal top in conductive foam, as this will drain the lithium button-cell battery. As Figure 3 shows, the static memory array and the quartz controlled clock oscillator of the M48T559Y are integrated on one silicon chip. The
two circuits are interconnected at the upper eight memory locations to provide user accessible BYTEWIDETM clock information in the bytes with addresses 1FF8h-1FFFh. The clock locations contain the year, month, date, day, hour, minute, and second in 24 hour BCD format. Corrections for 28, 29 (leap year), 30, and 31 day months are made automatically. Byte 1FF8h is the clock control register. This byte controls user access to the clock information and also stores the clock calibration setting. The eight clock bytes are not the actual clock counters themselves; they are memory locations consisting of BiPORTTM read/write memory cells. The M48T559Y includes a clock control circuit which updates the clock bytes with current infor-x 8 SRAM ARRAY LITHIUM CELL VOLTAGE SENSE AND SWITCHING CIRCUITRY VPFD
Mode Deselect Write Read Deselect VSO to VPFD (min) (2) VSO to 5.5V VCC E VIH VIL VIH VIL VIH VIL VIH X AD0-AD7 High Z DIN DOUT High Z High Z High Z Power Standby (3) Active CMOS Standby Battery Back-up Mode
Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage. 2. See Table 7 for details. AS0, AS1 active when E is high and VCC > V PFD.
mation once per second. The information can be accessed by the user in the same manner as any other location in the static memory array. The M48T559Y also has its own Power-fail Detect circuit. The control circuitry constantly monitors the single 5V supply for an out of tolerance condition.
When CC is out of tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system operation brought on by low VCC. As VCC falls below approximately 3V, the control circuitry connects the battery which maintains data and clock operation until valid power returns.
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