|Category||Memory => SRAM|
|Description||3.3v-5v 4 Mbit 512kb x8 Timekeeper SRAM|
|Company||ST Microelectronics, Inc.|
|Datasheet||Download M48T513V-70CS1 datasheet
INTEGRATED ULTRA LOW POWER SRAM, REAL TIME CLOCK, POWER-FAIL CONTROL CIRCUIT, BATTERY, and CRYSTAL YEAR 2000 COMPLIANT BCD CODED CENTURY, YEAR, MONTH, DAY, DATE, HOURS, MINUTES, and SECONDS BATTERY LOW WARNING FLAG AUTOMATIC POWER-FAIL CHIP DESELECT and WRITE PROTECTION TWO WRITE PROTECT VOLTAGES: (VPFD = Power-fail Deselect Voltage) M48T513Y: 4.2V VPFD M48T513V: 2.7V VPFD 3.0V
CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES SOFTWARE CONTROLLED CLOCK CALIBRATION for HIGH ACCURACY APPLICATIONS 10 YEARS of DATA RETENTION and CLOCK OPERATION in the ABSENCE of POWER SELF CONTAINED BATTERY and CRYSTAL in DIP PACKAGE MICROPROCESSOR POWER-ON RESET (Valid even during battery back-up mode) PROGRAMMABLE ALARM OUTPUT ACTIVE in BATTERY BACK-UP MODE SURFACE MOUNT CHIP SET PACKAGING INCLUDES a 44-PIN SOIC and a 32-LEAD TSOP (SNAPHAT TOP TO BE ORDERED SEPARATELY) SOIC PACKAGE PROVIDES DIRECT CONNECTION for a SNAPHAT TOP WHICH CONTAINS the BATTERY and CRYSTAL SNAPHAT® HOUSING (BATTERY/CRYSTAL) IS REPLACEABLE
G W WDI RST RSTIN IRQ/FT VCC VSS Address Inputs Data Inputs / Outputs Chip Enable Input Output Enable Input Write Enable Input Watchdog input Reset Output (open drain) Reset Input Interrupt / Frequency Test Output (open drain) Supply Voltage Ground
Symbol TA TSTG V IO VCC IO PD Parameter Ambient Operating Temperature Storage Temperature (VCC Off, Oscillator Off) Input or Output Voltages M48T513Y Supply Voltage M48T513V Output Current Power Dissipation mA W Value 0.3 to VCC to 7.0 Unit °C V
Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect reliability. 2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).
CAUTION: Negative undershoots below 0.3V are not allowed on any pin while in the Battery Back-up mode.
DESCRIPTION The M48T513Y/V TIMEKEEPER RAM x 8 non-volatile static RAM and real time clock, with programmable alarms and a watchdog timer. The special DIP package provides a fully integrated battery back-up memory and real time clock solution. The M48T513Y/V directly replaces industry standard x 8 SRAM. It also provides the non-volatility of Flash without any requirement for special write timing or limitations on the number of writes that can be performed.
For surface mount environments ST provides a Chip Set solution consisting a 44 pin 330mil SOIC TIMEKEEPER Supervisor (M48T201V/Y) and a 32 pin TSOP Type x 20mm) LPSRAM (M68Z512/W) packages. The 44 pin 330mil SOIC provides sockets with gold plated contacts at both ends for direct connection to a separate SNAPHAT housing containing the battery.LITHIUM CELL VOLTAGE SENSE AND SWITCHING CIRCUITRY VPFD
The unique design allows the SNAPHAT battery package to be mounted on top of the SOIC package after the completion of the surface mount process. Insertion of the SNAPHAT housing after reflow prevents potential battery damage due to the high temperatures required for device surfacemounting. The SNAPHAT housing is keyed to prevent reverse insertion. The SNAPHAT battery package is shipped separately in plastic anti-static tubes or in Tape & Reel form. The part number is "M4Txx-BR12SH1". Figure 3 illustrates the static memory array and the quartz controlled clock oscillator. The clock locations contain the century, year, month, date, day, hour, minute, and second in 24 hour BCD format. Corrections for 28, 29 (leap year), 30, and 31 day months are made automatically. The nine clock bytes (7FFFFh-7FFF9h and 7FFF1h) are not the actual clock counters, they are memory locations consisting of BiPORTTM read/write memory cells within the static RAM array. The M48T513Y/V includes a clock control circuit which updates the clock bytes with current information once per second. The information can be accessed by the user in the same manner as any
other location in the static memory array. Byte 7FFF8h is the clock control register. This byte controls user access to the clock information and also stores the clock calibration setting. Byte 7FFF7h contains the watchdog timer setting. The watchdog timer can generate either a reset or an interrupt, depending on the state of the Watchdog Steering bit (WDS). Bytes 7FFF6h-7FFF2h include bits that, when programmed, provide for clock alarm functionality. Alarms are activated when the register content matches the month, date, hours, minutes, and seconds of the clock registers. Byte 7FFF1h contains century information. Byte 7FFF0h contains additional flag information pertaining to the watchdog timer, the alarm condition and the battery status. The M48T513Y/V also has its own Power-Fail Detect circuit. This control circuitry constantly monitors the supply voltage for an out of tolerance condition. When VCC is out of tolerance, the circuit write protects the TIMEKEEPER register data and external SRAM, providing data security in the midst of unpredictable system operation. As VCC falls, the control circuitry automatically switches to the battery, maintaining data and clock operation until valid power is restored.
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