|Description||Single-chip 8-bit Microcontroller|
|Company||Philips Semiconductors (Acquired by NXP)|
|Datasheet||Download P83C557E6EBB/YYY datasheet
80C51 central processing unit × 8 ROM, expandable externally to 64 Kbytes ROM Code protection × 8 RAM, expandable externally to 64 Kbytes Two standard 16-bit timer/counters An additional 16-bit timer/counter coupled to four capture registers
The P80C557E6/P83C557E6 (hereafter generically referred as P8xC557E6) single-chip 8-bit microcontroller is manufactured in an advanced CMOS process and is a derivative of the 80C51 microcontroller family. The P8xC557E6 has the same instruction set as the 80C51. Three versions of the derivative exist:
Two 8-bit resolution, pulse width modulation outputs Five 8-bit I/O ports plus one 8-bit input port shared with analogI2C-bus serial I/O port with byte oriented master and slave
P83C557E6 48 Kbytes mask programmable ROM P80C557E6 ROMless version of the P83C557E6
Full-duplex UART compatible with the standard 80C51 On-chip watchdog timer 15 interrupt sources with 2 priority levels to 6 external sources
Extended temperature range to +85 °C) 5.5 V supply voltage range Frequency range for 80C51family standard oscillator: 3.5 MHz to
The P8xC557E6 contains a non-volatile 48 Kbytes mask programmable ROM (P83C557E6), a volatile × 8 read/write data memory, five 8-bit I/O ports, one 8-bit input port, two 16-bit timer/event counters (identical to the timers of the 80C51), an additional 16-bit timer coupled to capture and compare latches, a 15-source, two-priority-level, nested interrupt structure, an 8-input ADC, a dual DAC pulse width modulated interface, two serial interfaces (UART and I2C-bus), a "watchdog" timer, an on-chip oscillator and timing circuits. For systems that require extra capability the P8xC557E6 can be expanded using standard TTL compatible memories and logic. In addition, the P8xC557E6 has two software selectable modes of power reduction Idle Mode and power-down mode. The Idle Mode freezes the CPU while allowing the RAM, timers, serial ports, and interrupt system to continue functioning. The power-down mode saves the RAM contents but freezes the oscillator, causing all other chip functions to be inoperative. The device also functions as an arithmetic processor having facilities for both binary and BCD arithmetic as well as bit-handling capabilities. The instruction set consists of over 100 instructions: 49 one-byte, 45 two-byte, and 17 three- byte. With a 16 MHz system clock, 58% of the instructions are executed 0.75 µs and in 1.5 µs. Multiply and divide instructions require 3 µs.
Seconds Timer Software enable/disable of ALE output pulse Electromagnetic compatibility improvements Wakeup from Powerdown by external or seconds interrupt
PACKAGE EXTENDED TYPE NUMBER NAME ROMless P80C557E6EBB P80C557E6EFB ROM coded P83C557E6EFB/YYY1 QFP80 Plastic Quad Flat Pack; 80 leads Plastic Quad Flat Pack; 80 leads +85 QFP80 Plastic Quad Flat Pack; 80 leads Plastic Quad Flat Pack; 80 leads to +85 DESCRIPTION CODE FREQUENCY RANGE (MHz) TEMPERATURE RANGE (°C)
2 A8-15 PARALLEL I/O PORTS AND EXTERNAL BUS SERIAL UART PORT 8-BIT PORTS FOUR 16-BIT CAPTURE LATCHES T2 16-BIT TIMER/ EVENT COUNTERS T2 16-BIT COMPARATORS WITH REGISTERSALTERNATE FUNCTION OF PORT0 ALTERNATE FUNCTION OF PORT1 ALTERNATE FUNCTION OF PORT2
ALTERNATE FUNCTION OF PORT 3 ALTERNATE FUNCTION OF PORT 4 ALTERNATE FUNCTION OF PORT 5
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