Details, datasheet, quote on part number: P83C554SFBD
PartP83C554SFBD
CategoryLogic => Clock Drivers/Distribution
Description80c51 8-bit Microcontroller . 6 Clock Operation 16k/512 Otp/rom/romless, 7 Channel 10 Bit A/D, I2c, Pwm, Capture/compare, High I/o, 64l LQFP
CompanyPhilips Semiconductors (Acquired by NXP)
DatasheetDownload P83C554SFBD datasheet
  

 

Features, Applications

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
Preliminary specification Replaces data of 1999 Apr 07 IC20 Data Handbook 2000 Nov 10
DESCRIPTION

This data sheet describes the 6 clock version of the 8xC554. This device is only available in 64L LQFP. The 8xC554 Single-Chip 8-Bit Microcontroller is manufactured in an advanced CMOS process and is a derivative of the 80C51 microcontroller family. The 87C554 has the same instruction set as the 80C51. Three versions of the derivative exist:

80C51 central processing unit 8 EPROM expandable externally to 64k bytes An additional 16-bit timer/counter coupled to four capture registers

FEATURES

The 87C554 contains 8 non-volatile EPROM, 8 read/write data memory, five 8-bit I/O ports, one 8-bit input port, two 16-bit timer/event counters (identical to the timers of the 80C51), an additional 16-bit timer coupled to capture and compare latches, a 15-source, four-priority-level, nested interrupt structure, an 7-input ADC, a dual DAC pulse width modulated interface, two serial interfaces (UART and I2C-bus), a "watchdog" timer and on-chip oscillator and timing circuits. For systems that require extra capability, the 8xC554 can be expanded using standard TTL compatible memories and logic. In addition, the 8xC554 has two software selectable modes of power reduction--idle mode and power-down mode. The idle mode freezes the CPU while allowing the RAM, timers, serial ports, and interrupt system to continue functioning. Optionally, the ADC can be operated in Idle mode. The power-down mode saves the RAM contents but freezes the oscillator, causing all other chip functions to be inoperative. The device also functions as an arithmetic processor having facilities for both binary and BCD arithmetic plus bit-handling capabilities. The instruction set consists of over 100 instructions: 49 one-byte, 45 two-byte, and 17 three-byte. With an 8 MHz crystal, 58% of the instructions are executed 0.75 s and in 1.5 s. Multiply and divide instructions require 3 s.

Two standard 16-bit timer/counters 8 RAM, expandable externally to 64k bytes Capable of producing eight synchronized, timed outputs A 10-bit ADC with seven multiplexed analog inputs Fast 8-bit ADC option at 16 MHz Two 8-bit resolution, pulse width modulation outputs Five 8-bit I/O ports plus one 8-bit input port shared with analog

I2C-bus serial I/O port with byte oriented master and slave

On-chip watchdog timer Extended temperature ranges Full static operation to 16 MHz Operating voltage range: to 8 MHz) and

4 level priority interrupt 15 interrupt sources Full-duplex enhanced UART
Framing error detection Automatic address recognition
Clock can be stopped and resumed Idle mode Power down mode

Second DPTR register EMI reduction 6 clock operation and ALE inhibit Programmable I/O pins Wake-up from power-down by external interrupts Software reset Power-on detect reset ADC charge pump disable ONCE mode ADC active in Idle mode

OTP/EPROM P87C554SBBD P87C554SFBD ROM P83C554SBBD P83C554SFBD ROMless P80C554SBBD P80C554SFBD TEMPERATURE C AND PACKAGE to +70, Low Profile Quad Flat Package to +85, Low Profile Quad Flat Package FREQ. (MHz) 16 DRAWING NUMBER SOT3142

DEVICE NUMBER P87C554 OTP P83C554 ROM P80C554 ROMless = 16 MHz OPERATING FREQUENCY MAX TEMPERATURE RANGE to +85_C PACKAGE

XTAL2 EA ALE PSEN 2 A8-15 PARALLEL I/O PORTS AND EXTERNAL BUS SERIAL UART PORT 8-BIT PORT FOUR 16-BIT CAPTURE LATCHES T0, T1 TWO 16-BIT TIMER/EVENT COUNTERS PROGRAM MEMORY x 8 OTP/ROM DATA MEMORY x 8 RAM DUAL PWM ADC SERIAL I2C PORT

ALTERNATE FUNCTION OF PORT 0 ALTERNATE FUNCTION OF PORT 1 ALTERNATE FUNCTION OF PORT 2
ALTERNATE FUNCTION OF PORT 3 ALTERNATE FUNCTION OF PORT 4 ALTERNATE FUNCTION OF PORT 5

 

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