|Category||Logic => Gates => Complex Gates => CMOS/BiCMOS->4000 Family|
|Datasheet||Download MC14572UB datasheet
The MC14572UB hex functional gate is constructed with MOS Pchannel and Nchannel enhancement mode devices in a single monolithic structure. These complementary MOS logic gates find primary use where low power dissipation and/or high noise immunity is desired. The chip contains four inverters, one NOR gate and one NAND gate.
PDIP16 P SUFFIX CASE 648 MC14572UBCP AWLYYWW SOIC16 D SUFFIX CASE SOEIAJ16 F SUFFIX CASE 966 MC14572UB ALYW 1 14572U AWLYWW
Diode Protection on All Inputs Single Supply Operation Supply Voltage Range = 3.0 Vdc to 18 Vdc NOR Input Pin Adjacent to VSS Pin to Simplify Use As An Inverter NAND Input Pin Adjacent to VDD Pin to Simplify Use As An Inverter NOR Output Pin Adjacent to Inverter Input Pin For OR Application NAND Output Pin Adjacent to Inverter Input Pin For AND Application Capable of Driving Two Lowpower TTL Loads or One LowPower Schottky TTL Load over the Rated Temperature RangeMAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)
Symbol VDD Vin, Vout Iin, Iout PD TA Tstg TL Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) Input or Output Current (DC or Transient) per Pin Power Dissipation, per Package (Note 3.) Ambient Temperature Range Storage Temperature Range Lead Temperature (8Second Soldering) Value 0.5 to VDD +150 260 Unit mA A WL, L YY, Y WW, W= Assembly Location = Wafer Lot = Year = Work Week
mW °C Device MC14572UBF MC14572UBFEL Package SOIC16 SOEIAJ16 Shipping 2500/Tape & Reel See Note 1. See Note 1.
2. Maximum Ratings are those values beyond which damage to the device may occur. 3. Temperature Derating: Plastic "P and D/DW" Packages: 7.0 mW/_C From To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this highimpedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
1. For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative.OUTA INA OUTB INB OUTC IN 2C VSS VDD IN 1F OUTF INE OUTE IND OUTD
Input Voltage "0" Level (VO or 0.5 Vdc) (VO or 1.0 Vdc) (VO or 1.5 Vdc) "1" Level (VO or 4.5 Vdc) (VO or 9.0 Vdc) (VO or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Input Current Input Capacitance (Vin = 0) Quiescent Current (Per Package) Total Supply Current (5.) (6.) (Dynamic plus Quiescent, Per Package) (CL pF on all outputs, all buffers switching)
4. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. 5. The formulas given are for the typical characteristics only 6. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL 50) Vfk where: in µA (per package), CL in pF, V = (VDD VSS) in volts, f in kHz is input frequency, and = 0.006.
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