Details, datasheet, quote on part number: MC14569BDWR2
CategoryLogic => Counters
DescriptionProgrammable Divide-by-n Dual 4-Bit Binary/bcd Down Counter , Package: Pdip, Pins=16
CompanyON Semiconductor
DatasheetDownload MC14569BDWR2 datasheet
Cross ref.Similar parts: CD40102B, CD40103B, CD4017B, CD4017B-MIL, CD4020B, CD4020B-MIL, CD4060B, CD4060B-MIL, CD54HC393, CD54HC4017
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Features, Applications
MC14569B Programmable Divide-By-N Dual 4-Bit Binary/BCD Down Counter

The is a programmable divide­by­N dual 4­bit binary or BCD down counter constructed with MOS P­channel and N­channel enhancement mode devices (complementary MOS) in a monolithic structure. This device has been designed for use with the MC14568B phase comparator/counter in frequency synthesizers, phase­locked loops, and other frequency division applications requiring low power dissipation and/or high noise immunity.


Speed­up Circuitry for Zero Detection Each 4­Bit Counter Can Divide Independently in BCD or Binary

Mode Can be Cascaded With MC14526B for Frequency Synthesizer Applications All Outputs are Buffered Schmitt Triggered Clock Conditioning

MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1.)

Symbol VDD Vin, Vout Iin, Iout PD TA Tstg TL Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) Input or Output Current (DC or Transient) per Pin Power Dissipation, per Package (Note 2.) Ambient Temperature Range Storage Temperature Range Lead Temperature (8­Second Soldering) Value ­0.5 to VDD +150 260 Unit V

= Assembly Location = Wafer Lot = Year = Work Week

1. Maximum Ratings are those values beyond which damage to the device may occur. 2. Temperature Derating: Plastic "P and D/DW" Packages: ­ 7.0 mW/_C From To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high­impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.

Input Voltage "0" Level (VO or 0.5 Vdc) (VO or 1.0 Vdc) (VO or 1.5 Vdc) (VO or 4.5 Vdc) "1" Level (VO or 9.0 Vdc) (VO or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Input Current Input Capacitance (Vin = 0) Quiescent Current (Per Package) Total Supply Current (4.) (5.) (Dynamic plus Quiescent, Per Package) (CL pF on all outputs, all buffers switching) Source

3. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. 4. The formulas given are for the typical characteristics only 5. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL ­ 50) Vfk where: in µA (per package), CL in pF, V = (VDD ­ VSS) in volts, f in kHz is input frequency, and = 0.001.


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