|Description||32k X 8 Bit Static Random Access Memory|
|Company||Motorola Semiconductor Products|
|Datasheet||Download MCM6706AR datasheet
The a 262,144 bit static random access memory organized as 32,768 words of 8 bits, fabricated using high performance silicongate BiCMOS technology. Static design eliminates the need for external clocks or timing strobes. Output enable (G) is a special control feature that provides increased system flexibility and eliminates bus contention problems. The MCM6706AR meets JEDEC standards and is available in a revolutionary pinout 300 mil, 32lead surfacemount SOJ package. Single ± 10% Power Supply Fully Static No Clock or Timing Strobes Necessary All Inputs and Outputs Are TTL Compatible Three State Outputs Fast Access Times: = 8 ns Center Power and I/O Pins for Reduced Noise BLOCK DIAGRAM
DQ0 INPUT DATA CONTROL DQ7 A COLUMN I/O COLUMN DECODER ROW DECODER MEMORY MATRIX 512 ROWS x 8 COLUMNS VCC VSS
A14. Address W. Write Enable E. Chip Enable G. Output Enable DQ7. Data Input/Output VCC. 5 V Power Supply VSS. Ground NC. No ConnectionMode Not Selected Read Write I/O Pin HighZ Dout Din Cycle Read Cycle Write Cycle
Rating Power Supply Voltage Relative to VSS for Any Pin Except VCC Output Current Power Dissipation Temperature Under Bias Operating Temperature Symbol VCC Vin, Vout Iout PD Tbias TA Value 0.5 to VCC + 70 Unit W °C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this highimpedance circuit. This BiCMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained.
Storage Temperature Plastic Tstg 125 °C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.(VCC to 70°C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage (Operating Voltage Range) Input High Voltage Input Low Voltage Symbol VCC VIH VIL Min Typ 5.0 Max 5.5 VCC 0.3* 0.8 Unit V
* VIH (max) = VCC 0.3 V dc; VIH (max) = VCC V ac (pulse width 2.0 ns) I 30.0 mA. VIL (min) @ 30.0 mA; VIL (min) V ac (pulse width 2.0 ns) I 30.0 mA.
Parameter Input Leakage Current (All Inputs, Vin 0 to VCC) Output Leakage Current (E = VIH G = VIH, Vout 0 to VCC) Output High Voltage (IOH 4.0 mA) Output Low Voltage (IOL + 8.0 mA) Symbol Ilkg(I) Ilkg(O) VOH VOL Min 2.4 Max Unit µA V
Parameter AC Active Supply Current (Iout = 0 mA, VCC = max, f = fmax) AC Standby Current (E = VIH, VCC = max, f = fmax) CMOS Standby Current (VCC = max, = 0 MHz, E VCC 0.2 V, Vin VSS, or VCC 0.2 V) Symbol ICCA ISB1 ISB2 Unit mA Notes
NOTES: 1. Reference AC Operating Conditions and Characteristics for input and timing (VIH/VIL, tr/tf, pulse level 3.0 V, VIH = 3.0 V). 2. All addresses transition simultaneously low (LSB) and then high (MSB). 3. Data states are all zero.CAPACITANCE = 1.0 MHz, = 25°C, Periodically Sampled Rather Than 100% Tested)
Parameter Address Input Capacitance Control Pin Input Capacitance (E, G, W) I/O Capacitance Symbol Cin Cout Max 5 6 Unit pF
Input Timing Measurement Reference Level. 1.5 V Input Pulse Levels. 3.0 V Input Rise/Fall Time. 2 ns Output Timing Measurement Reference Level. 1.5 V Output Load. See Figure 1A
6 Parameter Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Output Hold from Address Change Chip Enable Low to Output Active Chip Enable High to Output HighZ Output Enable Low to Output Active Output Enable High to Output HighZ Symbol tAVAV tAVQV tELQV tGLQV tAXQX tELQX tEHQZ tGLQX tGHQZ Min Max Min Max Min Max Unit ns Notes 3
NOTES: W is high for read cycle. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles. 3. All read cycle timing is referenced from the last valid address to the first transitioning address. 4. At any given voltage and temperature, tEHQZ max < tELQX min, and tGHQZ max < tGLQX min, both for a given device and from device to device. 5. Transition is measured 200 mV from steadystate voltage with load of Figure 1B. 6. This parameter is sampled and not 100% tested. 7. Device is continuously selected (E = VIL, G = VIL). 8. Addresses valid prior to or coincident with E going low.
The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time (even though most devices do not require it). On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time.
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