Details, datasheet, quote on part number: MCM63Z818TQ133R
PartMCM63Z818TQ133R
Category
Description128k X 36 And 256k X 18 Bit Pipelined ZBT RAM Synchronous Fast Static RAM
CompanyMotorola Semiconductor Products
DatasheetDownload MCM63Z818TQ133R datasheet
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Features, Applications

The ZBT RAM a 4M­bit synchronous fast static RAM designed to provide zero bus turnaround. The ZBT RAM allows 100% use of bus cycles during back­to­back read/write and write/read cycles. The MCM63Z736 is organized as 128K words of 36 bits each and the MCM63Z818 is organized as 256K words of 18 bits each, fabricated with high performance silicon gate CMOS technology. This device integrates input registers, an output register, a 2­bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in communication applications. Synchronous design allows precise cycle control with the use of an external clock (CK). CMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability. Addresses (SA), data inputs (DQ), and all control signals except output enable (G) and linear burst order (LBO) are clock (CK) controlled through positive­ edge­triggered noninverting registers. Write cycles are internally self­timed and are initiated by the rising edge of the clock (CK) input. This feature eliminates complex off­chip write pulse generation and provides increased timing flexibility for incoming signals. For read cycles, pipelined SRAM output data is temporarily stored by an edge­ triggered output register and then released to the output buffers at the next rising edge of clock (CK). 3.3 V LVTTL and LVCMOS Compatible Access/7.5 ns Cycle (133 MHz) Access/10 ns Cycle (100 MHz) Selectable Burst Sequencing Order (Linear/Interleaved) Internally Self­Timed Write Cycle Two­Cycle Deselect Byte Write Control ADV Controlled Burst 100­Pin TQFP Package

ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc., and the architecture is supported by Micron Technology, Inc. and Motorola, Inc.

This document contains information on a new product. Specifications and information herein are subject to change without notice. REV 1 2/6/98

SE1 SE2 SBd SBc SBb SBa SE3 VDD VSS CK SW CKE G ADV NC SA DQc VDDQ VSS DQc VSS VDDQ DQc VDD VSS DQd VDDQ VSS DQd VSS VDDQ DQd LBO SA0 NC VSS VDD NC SA DQb VDDQ VSS DQb VSS VDDQ DQb VSS VDD VSS DQa VDDQ VSS DQa VSS VDDQ DQa

SE2 NC SBb SBa SE3 VDD VSS CK SW CKE G ADV SA NC VDDQ VSS NC DQb VSS VDDQ DQb VDD VSS DQb VDDQ VSS DQb NC VSS VDDQ NC LBO SA0 NC VSS VDD SA NC VDDQ VSS NC DQa VSS VDDQ DQa VSS VDD VSS DQa VDDQ VSS DQa NC VSS VDDQ NC


 

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