Details, datasheet, quote on part number: MCM63P818ZP66
PartMCM63P818ZP66
Category
Description128k X 36 And 256k X 18 Bit Pipelined Burstram Synchronous Fast Static RAM
CompanyMotorola Semiconductor Products
DatasheetDownload MCM63P818ZP66 datasheet
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Features, Applications

The MCM63P736 and MCM63P818 are 4M bit synchronous fast static RAMs designed to provide a burstable, high performance, secondary cache for the PowerPCTM and other high performance microprocessors. The MCM63P736 is organized as 128K words of 36 bits each and the MCM63P818 is organized as 256K words of 18 bits each. These devices integrate input registers, an output register, a 2­bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K). Addresses (SA), data inputs (DQx), and all control signals except output enable (G), sleep mode (ZZ), and linear burst order (LBO) are clock (K) controlled through positive­edge­triggered noninverting registers. Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst addresses can be generated internally by the MCM63P736 and MCM63P818 (burst sequence operates in linear or interleaved mode dependent upon the state of LBO) and controlled by the burst address advance (ADV) input pin. Write cycles are internally self­timed and are initiated by the rising edge of the clock (K) input. This feature eliminates complex off­chip write pulse generation and provides increased timing flexibility for incoming signals. Synchronous byte write (SBx), synchronous global write (SGW), and synchronous write enable (SW) are provided to allow writes to either individual bytes or to all bytes. The bytes are designated as "a", "b", etc. SBa controls DQa, SBb controls DQb, etc. Individual bytes are written if the selected byte writes SBx are asserted with SW. All bytes are written if either SGW is asserted or if all SBx and SW are asserted. For read cycles, pipelined SRAMs output data is temporarily stored by an edge­triggered output register and then released to the output buffers at the next rising edge of clock (K). The MCM63P736 and MCM63P818 operate from 3.3 V core power supply and all outputs operate 3.3 V power supply. All inputs and outputs are JEDEC standard JESD8­5 compatible. Access/7.5 ns Cycle (133 MHz) Access/10 ns Cycle (100 MHz) Access/15 ns Cycle (66 MHz) 3.3 V Core Power Supply, 3.3 V I/O Supply ADSP, ADSC, and ADV Burst Control Pins Selectable Burst Sequencing Order (Linear/Interleaved) Two­Cycle Deselect Timing Internally Self­Timed Write Cycle Byte Write and Global Write Control Sleep Mode (ZZ) PB1 Version 2.0 Compatible JEDEC Standard 119­Pin PBGA and 100­Pin TQFP Packages

The PowerPC name is a trademark of IBM Corp., used under license therefrom.

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. 10/8/97

WRITE REGISTER b 4/2 WRITE REGISTER c* DATA­IN REGISTER K DATA­OUT REGISTER

SE1 SE2 SBd SBc SBb SBa SE3 VDD VSS K SGW SW G ADSC ADSP ADV SA DQc VDDQ VSS DQc VSS VDDQ DQc NC VDD NC VSS DQd VDDQ VSS DQd VSS VDDQ DQd LBO SA0 NC VSS VDD NC SA TOP VIEW 119 BUMP PBGA TOP VIEW 100 PIN TQFP Not to Scale DQb VDDQ VSS DQb VSS VDDQ DQb VSS NC VDD ZZ DQa VDDQ VSS DQa VSS VDDQ DQa


 

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