Details, datasheet, quote on part number: MCM63P733ATQ133
PartMCM63P733ATQ133
Category
Description128k X 32 Bit Pipelined Burstram Synchronous Fast Static RAM
CompanyMotorola Semiconductor Products
DatasheetDownload MCM63P733ATQ133 datasheet
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Features, Applications

The a 4M­bit synchronous fast static RAM designed to provide a burstable, high performance, secondary cache for the PowerPCTM and other high performance microprocessors. It is organized as 128K words of 32 bits each, fabricated with high performance silicon gate CMOS technology. This device integrates input registers, an output register, a 2­bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K). CMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability. Addresses (SA), data inputs (DQx), and all control signals except output enable (G) and Linear Burst Order (LBO) are clock (K) controlled through positive­edge­triggered noninverting registers. Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst addresses can be generated internally by the MCM63P733A (burst sequence operates in linear or interleaved mode dependent upon state of LBO) and controlled by the burst address advance (ADV) input pin. Write cycles are internally self­timed and are initiated by the rising edge of the clock (K) input. This feature eliminates complex off­chip write pulse generation and provides increased timing flexibility for incoming signals. Synchronous byte write (SBx), synchronous global write (SGW), and synchronous write enable (SW) are provided to allow writes to either individual bytes or to all bytes. The four bytes are designated as "a", "b", "c", and "d". SBa controls DQa, SBb controls DQb, etc. Individual bytes are written if the selected byte writes SBx are asserted with SW. All bytes are written if either SGW is asserted or if all SBx and SW are asserted. For read cycles, pipelined SRAMs output data is temporarily stored by an edge­triggered output register and then released to the output buffers at the next rising edge of clock (K). The MCM63P733A operates from 3.3 V core power supply and all outputs operate 3.3 V power supply. All inputs and outputs are JEDEC standard JESD8­5 compatible. Access/7.5 ns Cycle (133 MHz) Access/8.5 ns Cycle (117 MHz) Access/10 ns Cycle (100 MHz) Access/11 ns Cycle (90 MHz) 3.3 V Core, Power Supply, 3.3 V I/O Supply ADSP, ADSC, and ADV Burst Control Pins Selectable Burst Sequencing Order (Linear/Interleaved) Internally Self­Timed Write Cycle Byte Write and Global Write Control Single­Cycle Deselect Sleep Mode (ZZ) 100­Pin TQFP Package

This document contains information on a new product. Specifications and information herein are subject to change without notice. REV 1 3/24/98

WRITE REGISTER b 4 WRITE REGISTER c DATA­IN REGISTER K DATA­OUT REGISTER

SE1 SE2 SBd SBc SBb SBa SE3 VDD VSS K SGW SW G ADSC ADSP ADV SA NC DQc VDDQ VSS DQc VSS VDDQ DQc NC VDD NC VSS DQd VDDQ VSS DQd VSS VDDQ DQd NC LBO SA0 NC VSS VDD SA NC DQb VDDQ VSS DQb VSS VDDQ DQb VSS NC VDD ZZ DQa VDDQ VSS DQa VSS VDDQ DQa NC


 

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