Details, datasheet, quote on part number: MCM63P636
PartMCM63P636
Category
Description64k X 36 Bit Pipelined Burstram Synchronous Fast Static RAM
CompanyMotorola Semiconductor Products
DatasheetDownload MCM63P636 datasheet
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Features, Applications

The a 2M­bit synchronous fast static RAM designed to provide burstable, high performance, secondary cache for advanced microprocessors. It is organized as 64K words of 36 bits each. This device integrates input registers, an output register, a 2­bit address counter, and a high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows for precise cycle control with the use of an external clock (K) and external strobe clock (SK). Addresses (SA), data inputs (DQx), and all control signals are clock (K) controlled through positive­edge­triggered noninverting registers. Data strobes STRBA, STRBB, and STRBB are strobe clock (SK) controlled through positive­edge­triggered non­inverting registers. Strobe clock, 180 degrees out of phase with clock (K), is only used with the data strobes such that they are centered with data output on read cycles. Burst sequences are initiated with ADS input pin, and subsequent burst addresses are generated internally by MCM63P636. Write cycles are internally self­timed and are initiated with address and control logic by the rising edge of the clock (K) input. This feature eliminates complex off­chip write pulse generation and provides increased timing flexibility for incoming signals. Special logic enables the memory to accept data on the rising edge of clock (K) a cycle after address and control signals. For read cycles, the SRAMs output data is temporarily stored by an edge­triggered output register and then released to the output buffers at the second rising edge of clock (K) for a read latency of three cycles. Data strobes rise and fall with SRAM output to help external devices receiving the data to latch the data. The MCM63P636 operates from 3.3 V core power supply, 2.0 V input power supply, and 2.0 V I/O power supply. These power supplies are designed so that power sequencing is not required. Access/4 ns Cycle (250 MHz) Access/4.4 ns Cycle (225 MHz) Access/5 ns Cycle (200 MHz) 200 mV VDD Supply, 2.0 V VDDI and VDDQ Supply Internally Self­Timed Late Write Cycle Three­Cycle Single­Read Latency Strobe Clock Input and Data Strobe Output Pins On­Chip Output Enable Control On­Chip Burst Advance Control Four­Tick Burst Power­On Reset Pin Low Power Stop Clock Operation Boundary Scan (PBGA Only) JEDEC Standard 153­Pin PBGA and 100­Pin TQFP Packages

This document contains information on a new product. Specifications and information herein are subject to change without notice.

1 A VSS VDDQ B DQa SE3 NC NU/VDD SA DQb VSS DQb VSS DQb VSS DQb VSS DQb VSS DQb VSS DQb VSS DQb VSS VDDQ VSS NU/VSS W DQa VSS DQa VSS DQa VDD VSS RESET VSS VDDQ DQb NC SA VDDQ VSS

DQb VDDQ VSS DQb VSS VDDQ DQb VSS STRBB VDD STRBB DQb VDDQ VSS DQb VSS VDDQ DQb

 

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