Details, datasheet, quote on part number: MCM63P631TQ4.5R
PartMCM63P631TQ4.5R
Category
Description64k X 32 Bit Pipelined Burstram Synchronous Fast Static RAM
CompanyMotorola Semiconductor Products
DatasheetDownload MCM63P631TQ4.5R datasheet
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Features, Applications

The a 2M bit synchronous fast static RAM designed to provide a burstable, high performance, secondary cache for the 68K Family, PowerPCTM, and PentiumTM microprocessors. It is organized as 64K words of 32 bits each. This device integrates input registers, an output register, a 2­bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K). CMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability. Addresses (SA), data inputs (DQx), and all control signals except output enable (G), sleep mode (ZZ), and Linear Burst Order (LBO) are clock (K) controlled through positive­edge­triggered noninverting registers. Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst addresses can be generated internally by the MCM63P631 (burst sequence operates in linear or interleaved mode dependent upon state of LBO) and controlled by the burst address advance (ADV) input pin. Write cycles are internally self­timed and are initiated by the rising edge of the clock (K) input. This feature eliminates complex off­chip write pulse generation and provides increased timing flexibility for incoming signals. Synchronous byte write (SBx), synchronous global write (SGW), and synchronous write enable SW are provided to allow writes to either individual bytes or to all bytes. The four bytes are designated as "a", "b", "c", and "d". SBa controls DQa, SBb controls DQb, etc. Individual bytes are written if the selected byte writes SBx are asserted with SW. All bytes are written if either SGW is asserted or if all SBx and SW are asserted. For read cycles, pipelined SRAMs output data is temporarily stored by an edge­triggered output register and then released to the output buffers at the next rising edge of clock (K). The MCM63P631 operates from 3.3 V power supply, all inputs and outputs are LVTTL compatible. 4.5 ns access 8.5 ns cycle (117 MHz) 4.5 ns access 10 ns cycle (100 MHz) 7 ns access 13.3 ns cycle (75 MHz) 8 ns access 15 ns cycle (66 MHz) Single 3.3 V Power Supply ADSP, ADSC, and ADV Burst Control Pins Selectable Burst Sequencing Order (Linear/Interleaved) Internally Self­Timed Write Cycle Byte Write and Global Write Control Sleep Mode (ZZ) PB1 Version 2.0 Compatible Single­Cycle Deselect Timing JEDEC Standard 100­Pin TQFP Package

The PowerPC name is a trademark of IBM Corp., used under license therefrom. Pentium is a trademark of Intel Corp.

This document contains information on a new product. Specifications and information herein are subject to change without notice.

WRITE REGISTER b 4 WRITE REGISTER c DATA­IN REGISTER K DATA­OUT REGISTER

 

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