Details, datasheet, quote on part number: MCM6323AYJ12R
PartMCM6323AYJ12R
Category
Description64k X 16 Bit 3.3 V Asynchronous Fast Static RAM
CompanyMotorola Semiconductor Products
DatasheetDownload MCM6323AYJ12R datasheet
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Features, Applications

The a 1,048,576 bit static random access memory organized as 65,536 words of 16 bits. Static design eliminates the need for external clocks or timing strobes; CMOS circuitry reduces power consumption and provides for greater reliability. The MCM6323A is equipped with chip enable (E), write enable (W), and output enable (G) pins, allowing for greater system flexibility and eliminating bus contention problems. Separate byte enable controls (LB and UB) allow individual bytes to be written and read. LB controls the 8 DQa bits, while UB controls the 8 DQb bits. The MCM6323A is available a 400 mil small­outline J­leaded (SOJ) package and a 44­lead TSOP Type II package in copper leadframe for optimum printed circuit board (PCB) reliability. Single 0.3 V Power Supply Fast Access Time: 15 ns Equal Address and Chip Enable Access Time All Inputs and Outputs are TTL Compatible Data Byte Control Fully Static Operation Power Operation: 140/135/130 mA Maximum, Active AC Industrial Temperature Option: + 85°C Part Number: SCM6323AYJ10A BLOCK DIAGRAM

G OUTPUT ENABLE BUFFER 7 ADDRESS BUFFERS 9 ROW COLUMN DECODER 8 HIGH BYTE OUTPUT ENABLE LOW BYTE OUTPUT ENABLE 8 HIGH BYTE OUTPUT BUFFER HIGH BYTE WRITE DRIVER 8 DQb 8 YJ PACKAGE 400 MIL SOJ CASE 919­01 TS PACKAGE 44­LEAD TSOP TYPE II CASE 924A­01

CHIP ENABLE BUFFER x 16 BIT MEMORY ARRAY 16 SENSE AMPS 8
LOW BYTE OUTPUT BUFFER 8 LOW BYTE WRITE DRIVER

A. Address Input E. Chip Enable W. Write Enable G. Output Enable UB. Upper Byte LB. Lower Byte DQa. Lower Data Input/Output DQb. Upper Data Input/Output VDD. 3.3 V Power Supply VSS. Ground NC. No Connection

HIGH BYTE WRITE ENABLE LOW BYTE WRITE ENABLE

This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice. REV 1 10/17/97

LB UB Mode Not Selected Output Disabled Output Disabled Low Byte Read High Byte Read Word Read Low Byte Write High Byte Write Word Write VDD Current ISB1, ISB2 IDDA DQa's High­Z Dout High­Z Dout Din High­Z Din DQb's High­Z Dout High­Z Din

Rating Supply Voltage on Any Pin Output Current per Pin Package Power Dissipation Temperature Under Bias Operating Temperature Storage Temperature Commerial Industrial Commerial Industrial Symbol VDD Vin Iout PD Tbias TA Tstg Value 0.5 to VDD + 150 Unit W °C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to these high­impedance circuits. This CMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained.

NOTES: 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. 2. All voltages are referenced to VSS. 3. Power dissipation capability will be dependent upon package characteristics and use environment.

(VDD to 70°C, Unless Otherwise Noted) (TA + 85°C for Industrial Temperature Offering) RECOMMENDED OPERATING CONDITIONS

Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol VDD VIH VIL Min Typ 3.3 Max 3.6 VDD 0.3** 0.8 Unit V

* VIL (min) 0.5 V dc; VIL (min) V ac (pulse width 20 ns) for I 20.0 mA. VIH (max) = VDD 0.3 V dc; VIH (max) = VDD V ac (pulse width 20 ns) for I 20.0 mA.

Parameter Input Leakage Current (All Inputs, Vin 0 to VDD) Output Leakage Current (E = VIH, Vout 0 to VDD) Output Low Voltage Output High Voltage (IOL + 4.0 mA) (IOL + 100 µA) (IOH ­ 4.0 mA) (IOH ­ 100 µA) Symbol Ilkg(I) Ilkg(O) VOL VOH Min 2.4 VDD ­ 0.2 Max VSS + 0.2 Unit µA V

Parameter AC Active Supply Current (Iout = 0 mA) (VDD = max, f = fmax) AC Standby Current (E = VIH, VDD = max, f = fmax) CMOS Standby Current (VDD = max, = 0 MHz, E VDD 0.2 V, Vin VSS V, or VDD 0.2 V) Commerical Industrial Commerical Industrial Commerical Industrial Symbol IDDA 6323A­12 6323A­15 Unit mA Notes 2

NOTES: 1. Typical current V. 2. Reference AC Operating Conditions and Characteristics for input and timing (VIH/VIL, tr/tf, pulse level 3.0 V, VIH 3.0 V, VIL = 0 V).

CAPACITANCE = 1.0 MHz, = 25°C, Periodically Sampled Rather Than 100% Tested)

Parameter Address Input Capacitance Control Input Capacitance Input/Output Capacitance Symbol Cin CI/O Typ Max 6 8 Unit pF


 

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