Details, datasheet, quote on part number: MCM6265CP25
PartMCM6265CP25
Category
Description8k X 9 Bit Fast Static RAM
CompanyMotorola Semiconductor Products
DatasheetDownload MCM6265CP25 datasheet
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Features, Applications

The MCM6265C is fabricated using Motorola's high­performance silicon­gate CMOS technology. Static design eliminates the need for external clocks or timing strobes, while CMOS circuitry reduces power consumption and provides for greater reliability. This device meets JEDEC standards for functionality and pinout, and is available in plastic dual­in­line and plastic small­outline J­leaded packages. Single ± 10% Power Supply Fully Static No Clock or Timing Strobes Necessary Fast Access Times: and 35 ns Equal Address and Chip Enable Access Times Output Enable (G) Feature for Increased System Flexibility and to Eliminate Bus Contention Problems Low Power Operation: 150 mA Maximum AC Fully TTL Compatible Three State Output

A11 DQ0 INPUT DATA CONTROL DQ8 COLUMN I/O COLUMN DECODER ROW DECODER MEMORY MATRIX 256 ROWS x 9 COLUMNS VCC VSS

­ A12. Address Input ­ DQ8. Data Input/Data Output W. Write Enable G. Output Enable E1, E2. Chip Enable VCC. Power Supply 5 V) VSS. Ground

E1 E2 Mode Not Selected Not Selected Output Disabled Read Write VCC Current ISB1, ISB2 ICCA Output High­Z Dout High­Z Cycle Read Cycle Write Cycle

Rating Power Supply Voltage Relative to VSS for Any Pin Except VCC Output Current Power Dissipation Temperature Under Bias Operating Temperature Symbol VCC Vin, Vout Iout PD Tbias TA Value 0.5 to VCC + 70 Unit W °C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to these high­impedance circuits. This CMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained.

Storage Temperature Plastic Tstg 125 °C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.

(VCC to +70°C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS

Parameter Supply Voltage (Operating Voltage Range) Input High Voltage Input Low Voltage * VIL (min) 0.5 V dc; VIL (min) V ac (pulse width 20 ns) VIH (max) = VCC 0.3 V dc; VIH (max) = VCC V ac (pulse width 20 ns) Symbol VCC VIH VIL Min Typ 5.0 Max 5.5 VCC 0.3** 0.8 Unit V

Parameter Input Leakage Current (All Inputs, Vin 0 to VCC) Output Leakage Current (E1 = VIH, E2 = VIL, G = VIH, Vout 0 to VCC) Output Low Voltage (IOL = 8.0 mA) Output High Voltage (IOH ­ 4.0 mA) Symbol Ilkg(I) Ilkg(O) VOL VOH Min 2.4 Max ±1 0.4 Unit µA V

Parameter AC Active Supply Current (Iout = 0 mA, VCC = Max, f = fmax) AC Standby Current (E1 = VIH E2 = VIL, VCC = Max, f = fmax) Standby Current (E1 VCC or E2 VSS 0.2 V, Vin VSS V or VCC 0.2 V) Symbol ICCA ISB1 ISB2 Unit mA

CAPACITANCE = 1 MHz, = 25°C, Periodically Sampled Rather Than 100% Tested)

Parameter Address Input Capacitance Control Pin Input Capacitance G, W) I/O Capacitance Symbol Cin CI/O Max 6 7 Unit pF

Input Timing Measurement Reference Level. 1.5 V Input Pulse Levels. 3.0 V Input Rise/Fall Time. 5 ns Output Timing Measurement Reference Level. 1.5 V Output Load. See Figure 1A Unless Otherwise Noted

­ 12 Parameter Read Cycle Time Address Access Time Enable Access Time Output Enable Access Time Output Hold from Address Change Enable Low to Output Active Enable High to Output High­Z Output Enable Low to Output Active Output Enable High to Output High­Z Power Up Time Symbol tAVAV tAVQV tELQV tGLQV tAXQX tELQX tEHQZ tGLQX tGHQZ tELICCH Min Max Min Max Min Max Min Max Min Max Unit ns Notes 3

Power Down Time tEHICCL ns NOTES: W is high for read cycle. 2. E1 and E2 are represented E in this data sheet. is of opposite polarity E. 3. All timings are referenced from the last valid address to the first transitioning address. 4. Addresses valid prior to or coincident with E going low. 5. At any given voltage and temperature, tEHQZ (max) is less than tELQX (min), and tGHQZ (max) is less than tGLQX (min), both for a given device and from device to device. 6. Transition is measured 500 mV from steady­state voltage with load of Figure 1B. 7. This parameter is sampled and not 100% tested. 8. Device is continuously selected (E1 = VIL, E2 = VIH, G = VIL).

The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time (even though most devices do not require it). On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time.


 

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