Details, datasheet, quote on part number: MC14597BCP
PartMC14597BCP
CategoryLogic
Description8-bit Bus-compatible Latches
CompanyMotorola Semiconductor Products
DatasheetDownload MC14597BCP datasheet
Cross ref.Similar parts: CD4099B-MIL, CD4724B, CD4724B-MIL
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Features, Applications

The MC14597B and MC14598B are 8­bit latches, one addressed with an internal counter and the other addressed with an external binary address. The 8 latch­outputs are high drive, three­state and bus line compatible. The drive capability allows direct applications with MPU systems such as the Motorola 6800 family. With a 3­bit address counter (clocked on the falling edge of Increment) selects the appropriate latch. The latches of the MC14598B are accessed via the Address pins, A0, A1, and A2. A Full Flag is provided on the MC14597B to indicate the position of the Address counter. All 8 outputs from the latches are available in parallel when Enable is in the low state. Data is entered into a selected latch from the Data pin when the Strobe is high. Master reset is available on both parts. Serial Data Input Three­State Bus Compatible Parallel Outputs Three­State Control Pin (Enable) TTL Compatible Input Open Drain Full Flag (Multiple Latch Wire­O Ring) Master Reset Level Shifting Inputs on All Except Enable Diode Protection All Inputs Supply Voltage Range 3.0 Vdc to 18 Vdc Capable of Driving TTL Over Rated Temperature Range With Fanout as Follows: 1 TTL Load 4 LSTTL Loads BLOCK DIAGRAMS

DATA STROBE 3­BIT ADDRESS COUNTER 7 INCREMENT VDD = 16 VSS = 8 FULL LOGIC 5 FULL ADDRESS DECODER

ENABLE 4 RESET DATA STROBE A1 8 ADDRESS A2 10 DECODER VDD = 18 VSS LATCHES 1 17 THREE 16 STATE 15 OUTPUT 14 BUFFERS D6 D7

©MOTOROLA Motorola, Inc. 1995 CMOS LOGIC DATA

Symbol VDD Vin Vout Iin, lout PD Tstg TL Parameter DC Supply Voltage Value Unit + 18.0 Input Voltage, Enable (DC or Transient) Input Voltage, All other Inputs (DC or Transient) Output Voltage (DC or Transient) Input or Output Current (DC or Transient), per Pin Power Dissipation, per Package Storage Temperature Lead Temperature (8­Second Soldering) 0.5 to VDD to VDD to VDD 150 260

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high­impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.

* Maximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: "P and D/DW" Packages: ­ 7.0 mW/C From To 125_C Ceramic "L" Packages: ­ 12 mW/_C From To 125_C

"1" Level Vin 0 or VDD Input Voltage** Enable "0" Level (VO or 0.5 Vdc) (VO or 1.0 Vdc) (VO or 1.5 Vdc) "1" Level (VO or 4.5 Vdc) (VO or 9.0 Vdc) (VO or 13.5 Vdc) Input Voltage "0" Level Other Inputs (VO or 0.5 Vdc) (VO or 1.0 Vdc) (VO or 1.5 Vdc) (VO or 4.5 Vdc) "1" Level (VO or 9.0 Vdc) (VO or 13.5 Vdc) Output Drive Current Source (Full Sink Only) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Input Current Three­State Leakage Current Input Capacitance (Vin = 0) Quiescent Current (Per Package) **Total Supply Current at an **External Load Capacitance **130 pF Sink

= (2.0 µA/kHz) f + IDD = (4.0 µA/kHz) f + IDD = (6.0 µA/kHz) f + IDD Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. The formulas given are for the typical characteristics only 25_C. IT

* The formulas given are for the typical characteristics only at 25_C. #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.


 

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