Details, datasheet, quote on part number: MC14582B
PartMC14582B
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Description
CompanyMotorola Semiconductor Products
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Features, Applications

The is a CMOS look­ahead carry generator capable of anticipating a carry across four binary adders or groups of adders. The device is cascadable to perform full look­ahead across n­bit adders. Carry, generate­carry, and propagate­carry functions are provided as enumerated in the pin designation table shown below. Expandable to any Number of Bits All Buffered Outputs Low Power Dissipation Diode Protection on All Inputs Supply Voltage Range = 3.0 Vdc to 18 Vdc Capable of Driving Two Low­power TTL Loads or One Low­Power Schottky TTL Load over the Rated Temperature Range

Symbol VDD Vin, Vout Iin, Iout PD Tstg TL Parameter DC Supply Voltage Input or Output Voltage (DC or Transient) Input or Output Current (DC or Transient), per Pin Power Dissipation, per Package Storage Temperature Lead Temperature (8­Second Soldering) Value Unit 0.5 to VDD 260 mW

* Maximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic "P and D/DW" Packages: ­ 7.0 mW/_C From To 125_C Ceramic "L" Packages: ­ 12 mW/_C From To 125_C

Designation P3 Cn Cn+x, Cn+y Cn+z G P Pin No's Function Active­Low Carry­Generate Inputs Active­Low Carry­Propagate Inputs Carry Input Carry Outputs Active­Low Group Carry­Generate Output Active­Low Group Carry­Propagate Output

©MOTOROLA Motorola, Inc. 1995 CMOS LOGIC DATA

#Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. The formulas given are for the typical characteristics only at 25_C.

To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL ­ 50) Vfk where: in µA (per package), CL in pF, V = (VDD ­ VSS) in volts, f in kHz is input frequency, and = 0.005.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.

Characteristic Output Rise and Fall Time tTLH, tTHL = (1.5 ns/pF) 25 ns tTLH, tTHL = (0.75 ns/pF) 12.5 ns tTLH, tTHL = (0.55 ns/pF) 9.5 ns Propagation Delay Time tPLH, tPHL = (1.7 ns/pF) 260 ns tPLH, tPHL = (0.66 ns/pF) 107 ns tPLH, tPHL = (0.5 ns/pF) 85 ns Symbol tTLH, tTHL VDD Min Typ Max 280 220 Unit ns tPLH, tPHL

* The formulas given are for the typical characteristics only at 25_C. #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.

Figure 1. Dynamic Power Dissipation Test Circuit and Waveform

 

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