|Company||Motorola Semiconductor Products|
|Datasheet||Download MC14581B datasheet
The is a CMOS 4bit ALU capable of providing 16 functions of two Boolean variables and 16 binary arithmetic operations on two 14bit words. The level of the mode control input determines whether the output function is logic or arithmetic. The desired logic function is selected by applying the appropriate binary word to the select inputs (S0 thru S3) with the mode control input high, while the desired arithmetic operation is selected by applying a low voltage to the mode control input, the required level to carry in, and the appropriate word to the select inputs. The word inputs and function outputs can be operated with either active high or active low data. Carry propagate (P) and carry generate (G) outputs are provided to allow a full lookahead carry scheme for fast simultaneous carry generation for the four bits in the package. Fast arithmetic operations on long words are obtainable by using the as a second order look ahead block. An inverted ripple carry input (Cn) and a ripple carry output (Cn+4) are included for ripple through operation. When the device is in the subtract mode (LHHL), comparison of two 4bit words present at the A and B inputs is provided using the = B output. It assumes a highlevel state when indicating equality. Also, when the ALU is in the subtract mode the Cn+4 output can be used to indicate relative magnitude as shown in this table:Data Level Active High Cn Cn+4 Magnitude A B A<B A>B B L SUFFIX CERAMIC CASE 623
Symbol VDD Parameter DC Supply Voltage Value Unit 150 260 Vin, Vout Iin, Iout PD Tstg TL Input or Output Voltage (DC or Transient) Input or Output Current (DC or Transient), per Pin Power Dissipation, per Package Storage Temperature Lead Temperature (8Second Soldering) 0.5 to VDD + 0.5
Functional and Pinout Equivalent to 74181. Diode Protection on All Inputs All Outputs Buffered Supply Voltage Range = 3.0 Vdc to 18 Vdc Capable of Driving Two Lowpower TTL Loads or One Lowpower Schottky TTL Load over the Rated Temperature Range
* Maximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic "P and D/DW" Packages: 7.0 mW/_C From To 125_C Ceramic "L" Packages: 12 mW/_C From To 125_C©MOTOROLA Motorola, Inc. 1995 CMOS LOGIC DATA
#Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. The formulas given are for the typical characteristics only 25_C. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL 50) Vfk where: in µA (per package), CL in pF, V = (VDD VSS) in volts, f in kHz is input frequency, and = 0.008.
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
Characteristic Output Rise and Fall Time tTLH, tTHL = (1.5 ns/pF) 25 ns tTLH, tTHL = (0.75 ns/pF) 12.5 ns tTLH, tTHL = (0.55 ns/pF) 9.5 ns Propagation Delay Time Sum in to Sum Out tPLH, tPHL = (1.7 ns/pF) 620 ns tPLH, tPHL = (0.66 ns/pF) 217 ns tPLH, tPHL = (0.5 ns/pF) 155 ns Sum in to Sum Out (Logic Mode) tPLH, tPHL = (1.7 ns/pF) 520 ns tPLH, tPHL = (0.66 ns/pF) 182 ns tPLH, tPHL = (0.5 ns/pF) 155 ns Sum = B tPLH, tPHL = (1.7 ns/pF) 870 ns tPLH, tPHL = (0.66 ns/pF) 297 ns tPLH, tPHL = (0.5 ns/pF) 220 ns Sum or G tPLH, tPHL = (1.7 ns/pF) 400 ns tPLH, tPHL = (0.66 ns/pF) 147 ns tPLH, tPHL = (0.5 ns/pF) 105 ns Sum to Cn+4 tPLH, tPHL = (1.7 ns/pF) 530 ns tPLH, tPHL = (0.66 ns/pF) 187 ns tPLH, tPHL = (0.5 ns/pF) 135 ns Carry in to Sum Out tPLH, tPHL = (1.7 ns/pF) 295 ns tPLH, tPHL = (0.66 ns/pF) 112 ns tPLH, tPHL = (0.5 ns/pF) 80 ns Carry to Cn+4 tPLH, tPHL = (1.7 ns/pF) 220 ns tPLH, tPHL = (0.66 ns/pF) 87 ns tPLH, tPHL = (0.5 ns/pF) 60 ns Symbol tTLH, tTHL VDD 10 15 Min Typ Max 10 15 tPLH, tPHL tPLH, tPHL 240 170 Unit ns tPLH, tPHL
* The formulas given are for the typical characteristics only at 25_C. #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.
AC Paths Test Sumin to Sumout Delay Time Sumin to P Delay Time Sumin to G Delay Time Sumin to Cn+4 Delay Time Cn to Sumout Delay Time to Cn+4 Delay Time Sumin = B Delay Time Sumin to Sumout Delay Time (Logic Mode) Inputs Cn A0 Outputs Any P G Cn+y Any F Cn+4 A=B DC Data Inputs To VSS Remaining A's Cn Remaining A's Cn All A's Cn All A's Cn All A's All A's All B's Remaining A's All A's To VDD All B's All B's Remaining B's Remaining B's All B's All B's Cn Mode Add Sub Exclusive OR Fig. 3 Waveform
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