|Company||Motorola Semiconductor Products|
|Datasheet||Download MC14580B datasheet
The by 4 multiport register useful in small scratch pad memories, arithmetic operations when coupled with an adder, and other data storage applications. It allows independent reading of any two words (or the same word at both outputs) while writing into any one of four words. Address changing and data entry occur on the rising edge of the clock. When the write enable input is low, the contents of any word may be accessed but not altered. No Restrictions on Clock Input Rise or Fall Times 3State Outputs Single Phase Clocking Supply Voltage Range = 3.0 Vdc to 18 Vdc Capable of Driving Two Lowpower TTL Loads or one Lowpower Schottky TTL Load Over the Rated Temperature Range Pin Compatible with CD40108 MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol VDD Vin, Vout Iin, Iout PD Tstg TL Parameter DC Supply Voltage Input or Output Voltage (DC or Transient) Input or Output Current (DC or Transient), per Pin Power Dissipation, per Package Storage Temperature Lead Temperature (8Second Soldering) L SUFFIX CERAMIC CASE 623Q2A Q3A WRITE 0 WRITE 1 READ 1B READ 0B VSS VDD D2 D3 CLOCK WE READ 1A READ 0A
* Maximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic "P and D/DW" Packages: 7.0 mW/_C From To 125_C Ceramic "L" Packages: 12 mW/_C From To 125_C©MOTOROLA Motorola, Inc. 1995 CMOS LOGIC DATA
#Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. The formulas given are for the typical characteristics only 25_C. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL 50) Vfk where: in µA (per package), CL in pF, V = (VDD VSS) in volts, f in kHz is input frequency, and = 0.004.
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
When loading repetitive highs, the output may glitch low momentarily after the rising edge of Clock. However, data integrity remains unaffected and data is valid after the propagation delays listed in the Switching Characteristics Table.
IDS Sink Current EXTERNAL POWER SUPPLY Position of S1 VGS = VDS = 2 VDD Vout Source Current 1 VDD Vout VDDFigure 1. Output Drive Current Test Circuit
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