Details, datasheet, quote on part number: MC14566BD
PartMC14566BD
CategoryCommunication
DescriptionIndustrial Time Base Generator
CompanyMotorola Semiconductor Products
DatasheetDownload MC14566BD datasheet
Cross ref.Similar parts: CD40102B, CD40103B, CD4017B, CD4017B-MIL, CD4020B, CD4020B-MIL, CD4040B, CD4060B, CD4060B-MIL, CD54HC393
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Features, Applications

The MC14566B industrial time base generator is constructed with MOS P­channel and N­channel enhancement mode devices in a single monolithic structure. This device consists a divide­by­10 ripple counter and or divide­by­6 ripple counter to permit stable time generation from 60 Hz line. By cascading this device as divide­by­60 counters, seconds and minutes can be counted and are available in BCD format at the circuit outputs. An internal monostable multivibrator is included whose output can be used as a reset or clock pulse providing additional frequency flexibility. Also a pin has been included to allow divide­by­5 counting for generating 1.0 Hz from European 50 Hz line. Pin 11 = VDD will cause ÷ 5. Negative Edge Triggered Counters for Ease of Cascading Pulse Shapers on Counter Inputs Accept Slow Input Rise Times Monostable Multivibrator Positive or Negative Edge Triggered Diode Protection on All Inputs Supply Voltage Range = 3.0 Vdc to 18 Vdc Capable of Driving Two Low­power TTL Loads or One Low­power Schottky TTL Load Over the Rated Temperature Range

Symbol VDD Vin, Vout Iin, Iout PD Tstg Parameter DC Supply Voltage Input or Output Voltage (DC or Transient) Input or Output Current (DC or Transient), per Pin Power Dissipation, per Package Storage Temperature Value Unit 0.5 to VDD + 150

TL Lead Temperature (8­Second Soldering) _C * Maximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic "P and D/DW" Packages: ­ 7.0 mW/_C From To 125_C Ceramic "L" Packages: ­ 12 mW/_C From To 125_C

©MOTOROLA Motorola, Inc. 1995 CMOS LOGIC DATA

#Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. The formulas given are for the typical characteristics only 25_C. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL ­ 50) Vfk where: in µA (per package), CL in pF, V = (VDD ­ VSS) in volts, f in kHz is input frequency, and = 0.001.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.

* The formulas given are for the typical characteristics only at 25_C. #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.

Figure 1. Power Dissipation Test Circuit and Waveform

 

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