Details, datasheet, quote on part number: LSI403Z
PartLSI403Z
CategoryDSPs (Digital Signal Processors)
Description
CompanyLSI Logic Corporation
DatasheetDownload LSI403Z datasheet
  

 

Features, Applications
LSI403Z Digital Signal Processor

Z S P TM A R C H I T E C T U R E P E R F O R M A N C E W I T H H I G H - E N D I N T E G R AT I O N

OVERVIEW

The LSI403Z is a low power 16-bit fixed-point digital signal processor (DSP) based on the LSI Logic ZSP400 DSP core. The device has been designed for applications requiring high throughput and flexibility coupled with a high speed I/O, such as Voice over Networks CPE/IAD devices and audio applications. The LSI403Z is capable of a maximum clock rate of 150 MHz for 600 MIPS peak per formance and sustained effective throughput of 300 DSP MIPS (MACs). The device is also software compatible with all other products in the ZSP architecture, and offers an unrivalled combination of code density, performance and ease of use.

FEATURES

150 MHz operation at 1.8V 2 high-speed serial/TDM ports

(T1/E1 framer, H.100/H.110 bit stream compatible)

Low power modes 32K words on-chip RAM, 2K

words on-chip ROM

8-channel DMA controller On-board PLL for clock generation 32-/16-bit external memory interface 2 on-board timers IEEE 1149.1-compliant JTAG port

The internal memory structure of the LSI403Z comprises of 16K words of on-chip instruction memory, 16K words of on-chip data memory, 2K words onchip boot ROM, and on-chip peripherals. Additionally, the boot ROM provides star t-up and self-test capabilities. Both synchronous and asynchronous devices are supported including sync-burst SRAM. The external memory is logically segmented into instruction, data, and peripheral spaces.

for real-time emulation

BENEFITS

300 MMAC sustained DSP

The DMA controller of the LSI403Z supports zero-overhead instruction or data transfers to or from the entire 32K words of internal RAM to the memory interface unit, host processor interface, or serial ports. The eight DMA channels are segmented between four "indexed" and four "non-indexed" channels. Indexed channels have the ability to multiplex and de-multiplex data. Indexed channels can also operate in non-indexed mode.

per formance at 150 MHz

Direct interfacing to standard

telecommunications interfaces, reducing system cost

High data throughput without

processor overhead

Low power per channel Flexibility to optimize power

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