Details, datasheet, quote on part number: LSH32JC20
PartLSH32JC20
CategoryLogic => Level Shifters
Description32-bit Cascadable Barrel Shifter
CompanyLogic Devices Inc.
DatasheetDownload LSH32JC20 datasheet
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Features, Applications

DESCRIPTION

The a 32-bit high speed shifter designed for use in floating point normalization, word pack/ unpack, field extraction, and similar applications. It has 32 data inputs, and 16 output lines. Any shift configuration of the 32 inputs, including circular (barrel) shifting, left shifts with zero fill, and right shift with sign extend are possible. In addition, a built-in priority encoder is provided to aid floating point normalization. SHIFT ARRAY The 32 inputs to the LSH32 are applied a 32-bit shift array. The 32 outputs of this array are multiplexed down to 16 lines for presentation at the device outputs. The array may be configured such that any contiguous 16-bit field (including wraparound of the 32 inputs) may be presented to the output pins under control of the shift code field (wrap mode). Alternatively, the wrap feature may be disabled, resulting in zero or sign bit fill, as appropriate (fill mode). The shift code control assignments and the resulting input to output mapping for the wrap mode are shown in Table 1. Essentially the LSH32 is configured as a left shift device. That is, a shift code of 000002 results in no shift of the input field. A code of 000012 provides an effective left shift of 1 position, etc. When viewed as a right shift, the shift code corresponds to the two's complement of the shift distance, i.e., a shift code 111112 (­110) results in a right shift of one position, etc. When not in the wrap mode, the LSH32 fills bit positions for which there is no corresponding input bit. The fill value and the positions filled depend on the RIGHT/LEFT (R/L) direction pin. This pin is a don't care input when in wrap mode. For left shifts in fill mode, lower bits are filled with zero as shown in Table 2. For right shifts, however, the SIGN input is used as the fill value. Table 3 depicts the bits to be filled as a function of shift code for the right shift case. Note that the R/L input changes only the fill convention, and does not affect the definition of the shift code. In fill mode, as in wrap mode, the shift code input represents the number of shift positions directly for left shifts, but the two's complement of the shift code results in the equivalent right shift. However, for fill mode the R/L input can be viewed as the most

FEATURES

u 32-bit Input, 32-bit Output Multiplexed to 16 Lines u Full 0-31 Position Barrel Shift Capability u Integral Priority Encoder for 32-bit Floating Point Normalization u Sign-Magnitude or Two's Complement Mantissa Representation u 32-bit Linear Shifts with Sign or Zero Fill u Independent Priority Encoder Outputs for Block Floating Point u 68-pin PLCC, J-Lead

significant bit a 6-bit two's complement shift code, comprised of R/L concatenated with the SI4­SI0 lines. Thus a positive shift code (R/L = 0) results in a left shift of 0­31 positions, and a negative code (R/L 1) a right shift to 32 positions. The LSH32 can thus effectively select any contiguous 32-bit field out of a (sign extended and zero filled) 96-bit "input." OUTPUT MULTIPLEXER The shift array outputs are applied a 2:1 multiplexer controlled by the MS/LS select line. This multiplexer makes available at the output pins either the most significant or least significant 16 outputs of the shift array. PRIORITY ENCODER The 32-bit input bus drives a priority encoder which is used to determine the first significant position for purposes of normalization. The priority encoder produces a five-bit code representing the location of the first non-zero bit in the input word. Code assignment is such that the priority encoder output represents the number of shift positions required to left align the first non-zero bit of the input word. Prior to the priority encoder, the input bits are individually exclusive OR'ed with the SIGN input. This allows normalization in floating point systems using two's complement mantissa representation. A negative value in two's complement representation will cause the exclusive OR gates to invert the input data to the encoder. As a result the leading significant digit will always be "1." This affects only the encoder inputs; the shift array always operates on the raw input data. The priority encoder function table is shown in Table 4.

TABLE 1. WRAP MODE SHIFT CODE DEFINITIONS

FILL MODE SHIFT CODE DEFINITIONS LEFT SHIFT

FILL MODE SHIFT CODE DEFINITIONS RIGHT SHIFT

The NORM input, when asserted results in the priority encoder output driving the internal shift code inputs directly. It is exactly equivalent to routing the SO4 ­SO 0 outputs back to the SI4 ­SI0 inputs. The NORM input provides faster normalization of 32-bit data by avoiding the delay associated with routing the shift code off chip. When using the NORM function, the LSH32 should be placed in fill mode, with the R/L input low. APPLICATIONS EXAMPLES Normalization of mantissas to 32 bits can be accomplished directly by a single LSH32. The NORM input is asserted, and fill mode and left shift are selected. The normalized mantissa is then available at the device output in two 16-bit segments, under the control of the output data multiplexer select, the MS/LS. it is desirable to avoid the necessity of multiplexing output data in 16-bit segments, two LSH32 devices can be used in parallel. Both devices receive the same input word, with the MS/LS select line of one wired high, and the other low. Each device will then independently determine the shift distance required for normalization, and the full 32 bits of output data will be available simultaneously.



 

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