|Description||4-mbit 256k X16, 512k x8 Boot Block Flash Memory Family|
|Datasheet||Download AB28F400BX-B90 datasheet
x8 x16 Input Output Architecture A28F400BX-T A28F400BX-B For High Performance and High Integration 16-bit and 32-bit CPUs Optimized High Density Blocked Architecture One 16 KB Protected Boot Block Two 8 KB Parameter Blocks One 96 KB Main Block Three 128 KB Main Blocks Top or Bottom Boot Locations Extended Cycling Capability 1 000 Block Erase Cycles Automated Word Byte Write and Block Erase Command User Interface Status Register Erase Suspend Capability SRAM-Compatible Write Interface Automatic Power Savings Feature 1 mA Typical ICC Active Current in Static Operation
Very High-Performance Read 90 ns Maximum Access Time 45 ns Maximum Output Enable Time Low Power Consumption 25 mA Typical Active Read Current Deep Power-Down Reset Input Acts as Reset for Boot Operations Automotive Temperature Operation 125 C Write Protection for Boot Block Hardware Data Protection Feature Erase Write Lockout During Power Transitions Industry Standard Surface Mount Packaging JEDEC ROM Compatible 44-Lead PSOP 12V Word Byte Write and Block Erase VPP g 5% Standard ETOX TM III Flash Technology 5V Read
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Intel's 4-Mbit Flash Memory Family is an extension of the Boot Block Architecture which includes blockselective erasure automated write and erase operations and standard microprocessor interface The 4-Mbit Flash Memory Family enhances the Boot Block Architecture by adding more density and blocks x8 x16 input output control very high speed low power an industry standard ROM compatible pinout and surface mount packaging The 4-Mbit flash family is an easy upgrade from Intel's 2-Mbit Boot Block Flash Memory Family The Intel A28F400BX-T B are 16-bit wide flash memory offerings optimized to meet the rigorous environmental requirements of Automotive Applications These high density flash memories provide user selectable bus operation for either or 16-bit applications The A28F400BX-T and A28F400BX-B are 194 304-bit nonvolatile memories organized as either 524 288 bytes 262 144 words of information They are offered in 44Lead plastic SOP packages The x8 x16 pinout conforms to the industry standard ROM EPROM pinout Read and Write characteristics are guaranteed over the ambient temperature range 125 C These devices use an integrated Command User Interface (CUI) and Write State Machine (WSM) for simplified word byte write and block erasure The A28F400BX-T provide block locations compatible with Intel's MCS-186 family i860 TM and 80960CA microprocessors The A28F400BX-B provides compatibility with Intel's 80960KX and 80960SX families as well as other embedded microprocessors The boot block includes a data protection feature to protect the boot code in critical applications With a maximum access time 90 ns these 4-Mbit flash devices are very high performance memories which interface at zero-wait-state to a wide range of microprocessors and microcontrollers Manufactured on Intel's 0 8 micron ETOX TM III process the 4-Mbit flash memory family provides world class quality reliability and cost-effectiveness at the 4-Mbit density level
the algorithms and timings necessary for program and erase operations including verifications thereby unburdening the microprocessor or microcontroller Writing of memory data is performed in word or byte increments typically within 9 ms which a 100% improvement over previous flash memory products The Status Register (SR) indicates the status of the WSM and whether the WSM successfully completed the desired program or erase operation Maximum Access Time 90 ns (TACC) is achieved over the automotive temperature range 10% VCC supply range 5 5V) and 100 pF output load IPP maximum Program current 40 mA for x16 operation and 30 mA for x8 operation IPP Erase current 30 mA maximum VPP erase and programming voltage 12 6V (VPP g 5%) under all operating conditions Typical ICC Active Current mA is achieved The 4-Mbit boot block flash memory family is also designed with an Automatic Power Savings (APS) feature to minimize system battery current drain and allows for very low power designs Once the device is accessed to read array data APS mode will immediately put the memory in static mode of operation where ICC active current is typically 1 mA until the next read is initiated When the CE and RP pins are at VCC and the BYTE pin is at either VCC or GND the CMOS Standby mode is enabled where ICC is typically mA A Deep Power-Down Mode is enabled when the RP pin is at ground minimizing power consumption and providing write protection during power-up conditions ICC current during deep power-down mode 50 mA typical An initial maximum access time or Reset Time ns is required from RP switching until outputs are valid Equivalently the device has a maximum wake-up time 210 ns until writes to the Command User Interface are recognized When is at ground the WSM is reset the Status Register is cleared and the entire device is protected from being written to This feature prevents data corruption and protects the code stored in the device during system reset The system Reset pin can be tied RP to reset the memory to normal read mode upon activation of the Reset pin With on-chip program erase automation in the 4-Mbit family and the RP functionality for data protection when the CPU is reset and even if a program or erase command is issued the device will not recognize any operation until RP returns to its normal state
Throughout this datasheet the A28F400BX refers to both the A28F400BX-T and A28F400BX-B devices Section 1 provides an overview of the 4-Mbit flash memory family including applications pinouts and pin descriptions Section 2 describes in detail the specific memory organization for the A28F400BX Section 3 provides a description of the family's principles of operations Finally the family's operating specifications are described
The A28F400BX boot block flash memory family is a very high performance 194 304 bit) memory family organized as either (262 144 words) of 16 bits each (524 288 bytes) of 8 bits each Seven Separately Erasable Blocks including a Hardware-Lockable boot block (16 384 Bytes) Two parameter blocks (8 192 Bytes each) and Four main blocks (1 block 98 304 Bytes and 3 blocks 131 072 Bytes) are included on the 4-Mbit family An erase operation erases one of the main blocks in typically 3 seconds and the boot or parameter blocks in typically 1 5 seconds independent of the remaining blocks Each block can be independently erased and programmed 1 000 times The Boot Block is located at either the top (A28F400BX-T) or the bottom (A28F400BX-B) of the address map in order to accommodate different microprocessor protocols for boot code location The hardware lockable boot block provides the most secure code storage The boot block is intended to store the kernel code required for booting-up a system When the RP pin is between 11 4V and 12 6V the boot block is unlocked and program and erase operations can be performed When the RP pin at or below 6 5V the boot block is locked and program and erase operations to the boot block are ignored The A28F400BX products are available in the ROM EPROM compatible pinout and housed in the 44-Lead PSOP (Plastic Small Outline) package as shown in Figure 3 The Command User Interface (CUI) serves as the interface between the microprocessor or microcontroller and the internal operation of the A28F400BX flash memory Program and Erase Automation allows program and erase operations to be executed using a twowrite command sequence to the CUI The internal Write State Machine (WSM) automatically executes
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