|Category||Logic => Bus Interface => Bus Oriented Circuits|
|Title||Bus Oriented Circuits|
|Description||Fast CMOS Octal Latched Transceiver|
|Company||Integrated Device Technology, Inc.|
|Datasheet||Download IDT74FCT543ATEB datasheet
Low input and output leakage 1µ A (max.) Extended commercial range to +85°C CMOS power levels True TTL input and output compatibility VOH = 3.3V (typ.) VOL = 0.3V (typ.) Meets or exceeds JEDEC standard 18 specifications Product available in Radiation Tolerant and Radiation Enhanced versions Military product compliant to MIL-STD-883, Class B and DESC listed (dual marked) Available in DIP, SOIC, SSOP, QSOP, CERPACK, and LCC packages Std., A, C and D speed grades High drive outputs (-15mA IOH, 64mA IOL) Power off disable outputs permit "live insertion"
The is a non-inverting octal transceiver built using an advanced dual metal CMOS technology. This device contains two sets of eight D-type latches with separate input and output controls for each set. For data flow from to B, for example, the A-to-B Enable (CEAB) input must be low in order to enter data from or to take data from B0B7, as indicated in the Function Table. With CEAB low, a low signal on the A-to-B Latch Enable (LEAB) input makes the A-to-B latches transparent; a subsequent low-to-high transition of the LEAB signal puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB and OEAB both low, the 3-state B output buffers are active and reflect the data present at the output of the A latches. Control of data from A is similar, but uses the CEBA, LEBA and OEBA inputs.OEBA OEAB CEBA LEBA CEAB LEAB
DIP/ SOIC/ SSOP/ QSOP/ CERPACK TOP VIEW
Symbol VTERM(2) VTERM(3) TSTG IOUT Rating Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature DC Output Current Max. to +120 Unit °C mA
Pin Names OEAB OEBA CEAB CEBA LEAB LEBA A0A7 B0B7 Description A-to-B Output Enable Input (Active LOW) B-to-A Output Enable Input (Active LOW) A-to-B Enable Input (Active LOW) B-to-A Enable Input (Active LOW) A-to-B Latch Enable Input (Active LOW) B-to-A Latch Enable Input (Active LOW) A-to-B Data Inputs or B-to-A 3-State Outputs B-to-A Data Inputs or A-to-B 3-State Outputs
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed Vcc by +0.5V unless otherwise noted. 2. Inputs and Vcc terminals only. 3. Outputs and I/O terminals only.
Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Typ. 6 8 Max. 10 12 Unit pFNOTE: 1. This parameter is measured at characterization but not tested.
Inputs CEAB H L LEAB L H OEAB H L Latch Status A-to-B Storing Transparent Storing High Z Current A Inputs Previous* A Inputs High Z Output Buffers B0B7
NOTES: 1. * Before LEAB LOW-to-HIGH Transition H = HIGH Voltage Level L = LOW Voltage Level = Don't Care 2. A-to-B data flow shown; B-to-A flow control is the same, except using CEBA, LEBA and OEBA.
Following Conditions Apply Unless Otherwise Specified: Commercial: to +85°C, VCC ± 5%; Military: to +125°C, VCC ± 10%
Symbol VIH VIL IIH IIL IOZH IOZL II VIK VH ICC Parameter Input HIGH Level Input LOW Level Input HIGH Current(4) Input LOW Current(4) High Impedance Output Current (3-State output pins) (4) Input HIGH Current Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current VCC = Max., VI = VCC (Max.) VCC = Min., IIN = 18mA VCC = Max., VIN = GND or VCC = Max. Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VCC = Max. = 0.5V Min. 200 0.01 Max. mA µA Unit V µA
Symbol VOH Parameter Output HIGH Voltage Test Conditions(1) VCC = Min. IOH = 6mA MIL. VIN = VIH or VIL IOH = 8mA COM'L IOH = 12mA MIL. IOH = 15mA COM'L. VCC = Min. IOL = 48mA MIL. VIN = VIH or VIL IOL = 64mA COM'L. VCC = Max, VO = GND (3) VCC = 0V, VIN VO 4.5V Min. 60 Typ.(2) Max. mA µA Unit VOutput LOW Voltage Short Circuit Current Input/Output Power Off Leakage(5)
NOTES: 1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC 5.0V, +25°C ambient. 3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second. 4. The test limit for this parameter -55°C. 5. This parameter is guaranteed but not tested.
|Related products with the same datasheet|
|Some Part number from the same manufacture Integrated Device Technology, Inc.|
|IDT74FCT543ATL Fast CMOS Octal Latched Transceiver|
|IDT74FCT543ATPY Octal Latched Transceiver|
|IDT74FCT543C Fast CMOS Octal Latched Transceiver|
|IDT74FCT543CTQ Octal Latched Transceiver|
|IDT74FCT543D Fast CMOS Octal Latched Transceiver|
|IDT74FCT543DTQ Octal Latched Transceiver|
|IDT74FCT543E Fast CMOS Octal Latched Transceiver|
|IDT74FCT573 Fast CMOS Octal Transparent Latch|
|IDT74FCT573ASO Octal Latched Transceiver|
|IDT74FCT573AT Fast CMOS Octal Transparent Latch|
|IDT74FCT573ATPG Octal Latched Transceiver|
IDT54FCT841CTPY : High-performance CMOS Bus Interface Latches
IDT7140LA-100B : Multiport High Speed 1k X 8 Dual-port Static SRAM
IDT7140LA25JB : Multi-Ports 1K X 8 Dual-port RAM
IDT2308A-1 : NINE Output 3.3V Clock Buffer
IDT23S08E-1HDC : 3.3V ZERO Delay Clock Buffer, Spread Spectrum Compatible
IDT72V3670L15PFI : 3.3v High-density Supersync(tm) ii 36-bit Fifo
IDT7140LA100PFGI : 1K X 8 DUAL-PORT SRAM, 100 ns, CDIP48 Specifications: Memory Category: SRAM Chip ; Density: 8 kbits ; Number of Words: 1 k ; Bits per Word: 8 bits ; Package Type: DIP, SIDE BRAZED, DIP-48 ; Pins: 48 ; Logic Family: CMOS ; Supply Voltage: 5V ; Access Time: 100 ns ; Operating Temperature: -40 to 85 C (-40 to 185 F)
IDT7143LA20GG : 2K X 16 MULTI-PORT SRAM, 45 ns, CQFP68 Specifications: Memory Category: SRAM Chip ; Density: 33 kbits ; Number of Words: 2 k ; Bits per Word: 16 bits ; Package Type: QFP, QFP-68 ; Pins: 68 ; Logic Family: CMOS ; Supply Voltage: 5V ; Access Time: 45 ns ; Operating Temperature: 0 to 70 C (32 to 158 F)
7152MI-02LF : 67 MHz, OTHER CLOCK GENERATOR, PDSO8 Specifications: Device Type: Clock Generator ; Bus Interface: CMOS ; Package Type: Surface Mount, SOIC, 0.150 INCH, ROHS COMPLIANT, SOIC-8 ; Supply Voltage: 3 to 3.6 volts ; Frequency: 67 MHz ; Operating Temperature: -40 to 85 C (-40 to 185 F) ; Features / Standards: RoHS, Lead-Free