|Category||Timing Circuits => Clock Buffers|
|Company||Integrated Circuit System|
|Datasheet||Download 8545AG datasheet
4 LVDS outputs 2 LVCMOS clock inputs to support redundant or selectable frequency fanout applications Maximum output frequency: 650MHz Translates LVCMOS input signals to LVDS levels Output skew: 40ps (maximum) Part-to-part skew: 500ps (maximum) Propagation delay: 3.6ns (maximum) 3.3V operating supply to 70°C ambient operating temperature Industrial temperature information available upon request
The is a low skew, high performance 1-to-4 LVCMOS-to-LVDS clock fanout buffer and HiPerClockSTM a member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. Utilizing Low Voltage Differential Signaling (LVDS) the ICS8545 provides a low power, low noise, solution for distributing clock signals over controlled impedances 100 . The ICS8545 accepts a LVCMOS input level and translates to 3.3V LVDS output levels.
Guaranteed output and part-to-part skew characteristics make the ICS8545 ideal for those applications demanding well defined performance and repeatability.
Type Power Input Unused Input Power Output Pulldown Pullup Pulldown Description Power supply ground. Synchronizing clock enable. When HIGH, clock outputs follows clock input. When LOW, Q outputs are forced low, nQ outputs are forced high. LVCMOS / LVTTL interface levels. Clock select input. When HIGH, selects CLK2 input. When LOW, selects CLK1 input. LVCMOS / LVTTL interface levels. LVCMOS / LVTTL clock input. Unused pins. LVCMOS / LVTTL clock input. Output enable. Controls enabling and disabling of outputs Q0, nQ0 thru Q3, nQ3. Positive supply pins. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor 51 Test Conditions Minimum Typical Maximum 4 Units pF KOutputs Selected Source CLK1 CLK2 Low ACTIVE Hi Z High ACTIVE
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1. In the active mode, the state of the outputs are a function of the CLK1 and CLK2 inputs as described in Table 3B.
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