Details, datasheet, quote on part number: 8523AG
Part8523AG
CategoryTiming Circuits => Clock Buffers
Description
CompanyIntegrated Circuit System
DatasheetDownload 8523AG datasheet
  

 

Features, Applications

FEATURES

4 differential LVHSTL compatible outputs Selectable diffferential CLK, nCLK or LVPECL clock inputs CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL Maximum output frequency: 650MHz Translates any single-ended input signal to LVHSTL levels with resistor bias on nCLK input Output skew: 30ps (maximum) Part-to-part skew: 200ps (maximum) Propagation delay: 1.6ns (maximum) 3.3V core, 1.8V output operating supply to 70°C ambient operating temperature Industrial temperature information available upon request

The is a low skew, high performance 1-to-4 Differential-to-LVHSTL fanout buffer HiPerClockSTM and a member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS8523 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin.

Guaranteed output and part-to-part skew characteristics make the ICS8523 ideal for those applications demanding well defined performance and repeatability.

GND CLK_EN CLK_SEL CLK nCLK PCLK nPCLK nc VDD Q0 nQ0 VDDO Q2 nQ2 VDDO Q3 nQ3
Input Unused Power Output Power Output

Power supply ground. Synchronizing clock enable. When HIGH, clock outputs follow clock Pullup input. When LOW, Q outputs are forced low, nQ outputs are forced high. LVCMOS / LVTTL interface levels. Clock select input. When HIGH, selects differential PCLK, nPCLK Pulldown inputs. When LOW, selects CLK, nCLK inputs. LVCMOS / LVTTL interface levels. Pulldown Non-inver ting differential clock input. Pullup Inver ting differential clock input. Inver ting differential LVPECL clock input. No connect. Core supply pin. Differential output pair. LVHSTL interface levels. Output supply pins. Differential output pair. LVHSTL interface levels. Differential output pair. LVHSTL interface levels. Differential output pair. LVHSTL interface levels. Pulldown Non-inver ting differential LVPECL clock input.

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor 51 Test Conditions Minimum Typical Maximum 4 Units pF K

Inputs Outputs Selected Source CLK, nCLK PCLK, nPCLK CLK, nCLK Q0:Q3 Disabled; LOW Disabled; LOW Enabled nQ0:nQ3 Disabled; HIGH Disabled; HIGH Enabled

1 PCLK, nPCLK Enabled After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1. In the active mode, the state of the outputs are a function of the CLK , nCLK and PCLK, nPCLK inputs as described in Table 3B.

Inputs CLK or PCLK Biased; NOTE 1 Biased; NOTE 1 nCLK or nPCLK 0 1 Biased; NOTE 1 Biased; NOTE 1 Q0:Q3 LOW HIGH LOW HIGH LOW Outputs nQ0:nQ3 HIGH LOW HIGH LOW HIGH Input to Output Mode Differential to Differential to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Polarity Non Inver ting Non Inver ting Non Inver ting Non Inver ting Inver ting Inver ting

NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".


 

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