Details, datasheet, quote on part number: GM71VS17803CT/CLT-7
PartGM71VS17803CT/CLT-7
CategoryMemory => DRAM => EDO/FPM DRAM => 16 Mb
Description
CompanyHynix Semiconductor
DatasheetDownload GM71VS17803CT/CLT-7 datasheet
  

 

Features, Applications

Description

The GM71V(S)17803C/CL is the new generation dynamic RAM organized x 8 bit. GM71V(S)17803C/CL has realized higher density, higher performance and various functions by utilizing advanced CMOS process technology. The GM71V(S)17803C/CL offers Extended Data out(EDO) Page Mode as a high speed access mode. Multiplexed address inputs permit the to be packaged in standard 400 mil 28pin plastic SOJ, and standard 400mil 28pin plastic TSOP II. The package size provides high system bit densities and is compatible with widely available automated testing and insertion equipment.

Features

* 2,097,152 Words x 8 Bit Organization * Extended Data Out Mode Capability * Single Power Supply (3.3V+/-0.3V) * Fast Access Time & Cycle Time (Unit: ns)

* Low Power Active : 396/360/324mW (MAX) Standby : 7.2mW (CMOS level : MAX) 0.36mW (L-version : MAX) * RAS Only Refresh, CAS before RAS Refresh, Hidden Refresh Capability *All inputs and outputs TTL Compatible * 2048 Refresh * 2048 Refresh Cycles/128ms (L-version) * Self Refresh Operation (L-version) * Battery Back Up Operation (L-version)

Address Inputs Refresh Address Inputs Data Input/ Data Output Row Address Strobe Column Address Strobe

Read/Write Enable Output Enable Power (+3.3V) Ground No Connection

Ambient Temperature under Bias Storage Temperature Voltage on any Pin Relative to VSS Supply Voltage Relative to VSS Short Circuit Output Current Power Dissipation

Note: Operation at or above Absolute Maximum Ratings can adversely affect device reliability.
Supply Voltage Input High Voltage Input Low Voltage

Output Level Output "H" Level Voltage (IOUT = -2mA) Output Level Output "L" Level Voltage (IOUT = 2mA) Operating Current Average Power Supply Operating Current (RAS, CAS Cycling: tRC = tRC min) Standby Current (TTL) Power Supply Standby Current (RAS, CAS = VIH, DOUT = High-Z) RAS Only Refresh Current Average Power Supply Current RAS Only Refresh Mode (tRC = tRC min) EDO Page Mode Current Average Power Supply Current EDO Page Mode (tHPC = tHPC min) Standby Current (CMOS) Power Supply Standby Current (RAS, CAS >VCC - 0.2V, DOUT = High-Z) CAS-before-RAS Refresh Current (tRC = tRC min) 60ns 70ns

Battery Back Up Operating Current(Standby with CBR Ref.) (CBR refresh, tRC= 62.5us, tRAS<= 0.3us, DOUT=High-Z, CMOS Interface) Standby Current RAS = VIH CAS = VIL DOUT = Enable Self-Refresh Mode Current (RAS, CAS<= 0.2V, DOUT=High-Z, CMOS interface) Input Leakage Current Any Input (0V<= VIN<= 4.6V) Output Leakage Current (DOUT is Disabled, 0V<= VOUT<= 4.6V)

Note: 1. ICC depends on output load condition when the device is selected. ICC(max) is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH. 4. CAS L (<=0.2V) while RAS 5. L -version.


 

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