Details, datasheet, quote on part number: GM71VS16163CJ/CLJ-7
PartGM71VS16163CJ/CLJ-7
CategoryMemory => DRAM => EDO/FPM DRAM => 16 Mb
Description
CompanyHynix Semiconductor
DatasheetDownload GM71VS16163CJ/CLJ-7 datasheet
  

 

Features, Applications

Description

The GM71V(S)16163C/CL is the new generation dynamic RAM organized x 16 bit. GM71V(S)16163C/CL has realized higher density, higher performance and various functions by utilizing advanced CMOS process technology. The GM71V(S)16163C/CL offers Extended Data out(EDO) Mode as a high speed access mode. Multplexed address inputs permit the to be packaged in standard 400 mil 42pin plastic SOJ, and standard 400mil 44(50)pin plastic TSOP II. The package size provides high system bit densities and is compatible with widely available automated testing and insertion equipment.

Features

* 1,048,576 Words x 16 Bit Organization * Extended Data Out Mode Capability * Single Power Supply (3.3V+/-0.3V) * Fast Access Time & Cycle Time (Unit: ns)

* Low Power Active : 396/360/324/288mW (MAX) Standby : 7.2mW (MAX) 0.83mW (L-series : MAX) * RAS Only Refresh, CAS before RAS Refresh, Hidden Refresh Capability * All inputs and outputs TTL Compatible * 4096 Refresh * 4096 Refresh Cycles/128ms (L-series) * Self Refresh Operation (L-version) * Battery Back Up Operation (L-series) * 2 CAS byte Control

Address Inputs Refresh Address Inputs Data-In/Out Row Address Strobe Column Address Strobe
Write Enable Output Enable Power (+3.3V) Ground No Connection

Ambient Temperature under Bias Storage Temperature Voltage on any Pin Relative to VSS Supply Voltage Relative to VSS Short Circuit Output Current Power Dissipation

Supply Voltage Input High Voltage Input Low Voltage
Open Valid Open Undefined Valid Open

Standby Lower byte Upper byte Word Lower byte Upper byte Word Lower byte Upper byte Word Lower byte Upper byte Word CBR Refresh or Self Refresh (L-series) LAS-only Refresh cycle Read-modify -write cycle Delayed Write cycle Early write cycle Read cycle

Notes: 1. H: High (inactive) L: Low(active) L 2. tWCS 0ns Early write cycle tWCS < 0ns Delayed write cycle 3. Mode is determined by the OR fuction of the UCAS and LCAS. (Mode is set by earliest of UCAS and LCAS active edge and reset by the latest of UCAS and LCAS inactive edgs.) However write OPERATION and output HIZ control are done independently by each UACS,LCAS. ex. if RAS to L, UCAS = H, LCAS = L, then CAS-before-RAS refresh cycle is selected.


 

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GM71VS16163CCL-5
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GM71VS16163CJ/CLJ-5
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