Details, datasheet, quote on part number: AM29F002T-120JIB
Description2 Megabit ( 256 K X 8-bit ) CMOS 5.0 Volt-only Boot Sector Flash Memory
CompanyAdvanced Micro Devices, Inc.
DatasheetDownload AM29F002T-120JIB datasheet
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Features, Applications

2 Megabit x 8-Bit) CMOS 5.0 Volt-only Boot Sector Flash Memory

s Single power supply operation 5.0 Volt-only operation for read, erase, and program operations Minimizes system level requirements s High performance Access times as fast ns s Low power consumption (typical values at 5 MHz) 1 A standby mode current 20 mA read current 30 mA program/erase current s Flexible sector architecture One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and three 64 Kbyte sectors Supports full chip erase Sector Protection features: A hardware method of locking a sector to prevent any program or erase operations within that sector Sectors can be locked via programming equipment Temporary Sector Unprotect feature allows code changes in previously locked sectors s Top or bottom boot block configurations available s Embedded Algorithms Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors Embedded Program algorithm automatically writes and verifies data at specified addresses s Minimum 100,000 write cycle guarantee per sector s Package option 32-pin PDIP 32-pin TSOP 32-pin PLCC s Compatibility with JEDEC standards Pinout and software compatible with singlepower supply Flash Superior inadvertent write protection s Data# Polling and toggle bits Provides a software method of detecting program or erase operation completion s Erase Suspend/Erase Resume Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation s Hardware reset pin (RESET#) Hardware method to reset the device to reading array data (not available on Am29F002N)

The Am29F002 Family consists of 2 Mbit, 5.0 volt-only Flash memory devices organized as 262,144 bytes. The Am29F002 offers the RESET# function, the Am29F002N does not. The data appears DQ7 DQ0. The device is offered in 32-pin PLCC, 32-pin TSOP, and 32-pin PDIP packages. This device is designed to be programmed in-system with the standard system 5.0 volt V CC supply. PP is required for write or erase operations. The device can also be programmed in standard EPROM programmers. The standard device offers access times 70, 90, and 120 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. The device requires only a single 5.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm--an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm--an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved via programming equipment. The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory. (This feature is not available on the Am29F002N.) The system can place the device into the standby mode. Power consumption is greatly reduced in this mode. AMD's Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection.

Family Part Number Speed Option VCC 5% VCC 10% Max access time, ns (tACC) Max CE# access time, ns (tCE) Max OE# access time, ns (tOE) Am29F002/Am29F002N

Sector Switches Erase Voltage Generator Input/Output Buffers
PGM Voltage Generator Chip Enable Output Enable Logic STB Data Latch


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