Details, datasheet, quote on part number: MC145745D
PartMC145745D
Category
Description
CompanyN.A.
DatasheetDownload MC145745D datasheet
  

 

Features, Applications

The is a selectable modem chip compatible with ITU V.21 (300 baud full duplex asynchronous) and V.23 mode 2 (1200 baud half duplex asynchronous). The built­in differential line driver has the capability of driving 0 dBm into a 600 load with 5 V single power supply. This device also includes a DTMF generator, DTMF receiver, call­progress tone detector, answer tone generator, and a receive timing control circuit. Besides having a clock generator with a crystal oscillator connected to it, the device has a divider circuit to which input of a double frequency clock is possible from external sources, such as from a microcontroller unit (MCU). The serial control port (SCP) permits the MCU to access internal registers for exercising the built­in features. A low consumption device, the MC145745 integrates various functions in a small package. This modem IC is best suited for telemeter and other applications of this type. Conforms to ITU V.21 and V.23 Recommendations DTMF Generator and Receiver for all 16 Standard Digits Capable of Driving 0 dBm into a 600 Load (VCC 5 V) Automatic Gain Control (AGC) Amplifier for the DTMF Receiver Call­Progress Tone Detector Four­Wire Serial Data Interface (SCP) Programmable Transmission and Carrier Detection Levels FSK/DTMF Analog Loopback Self­Test Function Crystal Oscillator (3.579545 MHz) and Half Divider Circuit (7.159090 MHz) for External Inputs Operates in the Voltage Range 5.5 V Power Down Mode (ICC < 1 µA)

GND Vref CDA TLA TEST 1 RxD TxD CD CLKO X1 X2 ECLK PB0 GND VCC RxA TxA1 TxA2 TEST 2 SCPEN SCPCLK SCP Rx SCP Tx RESET PB2 PB1 VCC

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. REV 0 7/96

Rx AMP AND AGC CONTROL LOOPBACK PATH SMOOTHING FILTER AND Tx GAIN CONTROL 1/2

4 ANTI­ALIAS AND LOW­PASS FILTER TONE GENERATOR DTMF RECEIVER CPT DETECTOR FSK CARRIER DETECTOR FSK V.21 MODEM FSK V.23 MODEM TIMING CONTROL CIRCUIT

Pin Location Symbol GND Vref CDA Type Description Ground These are the ground pins of the digital and the analog circuits. The 0 V potential of the device is determined by the input voltage at these pins. Reference Analog Ground This pin provides the analog ground voltage VCC/2, which is regulated internally. This pin should be decoupled to GND with 0.1 µF and 100 µF capacitors. Carrier Detect Level Adjustment The detection level for FSK/call­progress tone is determined according to the voltage at this pin. When VCC 5 V and the carrier detection level bit (BR3:b1) of the SCP register 0, or when VCC 3.6 V and is 1, the CDA voltage is set V by the internal divider. This voltage sets the detection levels ON to OFF: ­ 44 dBm (typ) and OFF to ON: ­ 47 dBm (typ). This high impedance pin should be decoupled to GND with 0.1 µF capacitor. The carrier detection level is proportional to the terminal voltage at this pin. An external voltage may be applied to this pin to adjust the carrier detect threshold. The following equations may be used to find the CDA voltage requirements for a given threshold voltage. VCDA 256 x Von VCDA 362 x Voff Transmit Level Adjustment This pin is used to adjust the transmit carrier level which is determined by the resistor (RTLA) connected between this pin and GND. The maximum level is obtained when this pin is shorted to GND (RTLA = 0). Test Pins 1 and 2 These test pins are for manufacturer's use only. These pins should be left open in normal operation. Receive Data Output This pin is the receive data output. When the device is in the FSK mode, logic high on this pin indicates that the mark carrier frequency has been received from RxA, and the logic low indicates that the space carrier frequency has been received. Transmit Data Input This pin is the transmit data input. When the device is in the FSK mode, logic high on this pin generates the mark frequency at TxA1 and TxA2 output, and logic low generates the space frequency. Carrier Detect Output This pin outputs at low level if a valid FSK, DTMF, or CPTD signal is received. If the pin is at high level, the receive data output pin (RxD) is internally clamped at high level to avoid erroneous output of received data caused by line noise. Clock Output This pin provides a buffered 3.58 MHz clock output that can drive one CMOS device such as the MC74HC04. Crystal Oscillator Circuit Output A 3.579545 MHz ± 0.1% crystal oscillator is tied to this pin with the other end connected to X2. Crystal Oscillator Circuit Input A 3.579545 MHz ± 0.1% crystal oscillator is tied to this pin with the other end connected X1. X2 may be driven directly from an appropriate external clock source. External Clock Input ECLK is the input of double frequency, 7.159090 MHz 0.1%, of the reference clock. This pin must be connected to GND when not in use. DTMF Receive Data Parallel Output 0 (LSB) Pins 16, 17, and 18 are the DTMF receive data parallel output occurring together with the CD (Pin 8) data valid output. The outputs of these pins are valid as long as the CD pin is low. In power down modes 1 and 2, the DTMF receiver is disabled and these pins are in high impedance. Positive Power Supply These are the power supply pins for the digital and the analog circuits. These pins should be decoupled to GND with 0.1 µF and 100 µF capacitors. DTMF Receive Data Parallel Outputs 1, 2, and 3 (MSB) These pins are the DTMF receiver data parallel outputs. details. outputs See pin 13 for more details Reset A high to low trigger pulse applied to this pin sets all the registers in the default state. It should remain at high during normal operations. SCP Output Transmit Refer to Serial Control Port (SCP Interface) for additional information. SCP Receive Input Refer to Serial Control Port (SCP Interface) for additional information. SCP Clock Refer to Serial Control Port (SCP Interface) for additional information. SCP Enable Refer to Serial Control Port (SCP Interface) for additional information.


 

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