|Datasheet||Download M54HCT646 datasheet
HIGH SPEED fMAX = 60 MHz (TYP.) AT VCC 5 V LOW POWER DISSIPATION ICC 4 µA (MAX.) 25 °C COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN.) VIL = 0.8V (MAX) OUTPUT DRIVE CAPABILITY 15 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE IOH= IOL 6 mA (MIN.) BALANCED PROPAGATION DELAYS tPLH = tPHL PIN AND FUNCTION COMPATIBLE WITH 54/74LS646/648
DESCRIPTION The M74HCT646/648 are high speed CMOS OCTAL BUS TRANSCEIVERS AND REGISTERS, 2 (3-STATE) fabricated in silicon gate C MOS technology. They have the same high speed performance of LSTTL combined with true CMOS low power consumption. These devices consist of bus transceiver circuits with 3-state output, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the or B bus will be clocked into the registers on the lowto-high transition of the appropriate clock pin (Clock - or Clock BA). Enable (G) and direction (DIR) pins are provided to control the transceiver functions. In the transceiver mode, data present at the high-impedance port may be stored in either register or in both. The select controls (Select AB select BA) can multiplex stored and real-time (transparent mode) data. The direction control determines which bus will receive data when enable G is active (low). In the isolation mode (enable G high), "A" data may be stored in one register and/or "B" data may be stored in the other register. When an output function is disabled, the input function is still enabled and may be used to store and transmit data. Only one of the two buses, or B, may be driven at a time. All inputs are equipped with protection circuits against static discharge and transient excess voltage.This integrated circuit has input and output characteristics that are fully compatible with 54/74 LSTTL logic families. M74HCT devices are designed to directly interface HSC2MOS systems with TTL and NMOS components. They are also plug in replacements for LSTTL devices giving a reduction of power consumption.Note : In case of M54/74HCT646 output inverter marked at A bus and B bus are eliminated.
TRUTH TABLE HCT646 (The truth table for HCT648 is the same as this, but with the outputs inverted)
G DIR CAB CBA SAB SBA INPUTS Z INPUTS B INPUTS Z INPUTS FUNCTION Both the A bus and the B bus are inputs The output functions of the A and B bus are disabled Both the A and B bus are used for inputs to the internal flip-flops. Data at the bus will be stored on low to high transition of the clock inputs The A bus are inputs and the B bus are outputs The data at the A bus are displayed at the B bus The data at the A bus are displayed at the B bus. The data of the A bus are stored to the internal flip-flop on low to high transition of th clock pulse. The data stored to the internal flip-flop are dispayed at the B bus The data at the A bus are stored to the internal flipflop on low to high transition of the clock pulse. The states of the internal flip-flops output directly to the B bus The A bus are outputs and the B bus are inputs The data at the B bus are displayed at the A bus The data at the B bus are displayed at the A bus. The data of the B bus are stored to the internal flipflop on low to high transition of the clock pulse The data stored to the internal flip-flops are displayed at the B bus the data at the B bus are stored to the internal flipflop on low to high transition of the clock pulse. The states of the internal flip-flops output directly to the A bus
X : DON'T CARE Z : HIGH IMPEDANCE Qn : THE DATA STORED TO THE INTERNAL FLIP-FLOPS BY MOST RECENT LOW TO HIGH TRANSITION OF THE CLOCK INPUTS * : THE DATA AT THE A AND B BUS WILL BE STORED TO THE INTERNAL FLIP-FLOPS ON EVERY LOW TO HIGH TRANSITION OF THE CLOCK INPUTS
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