Details, datasheet, quote on part number: M54HCT573
PartM54HCT573
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Features, Applications
OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT HCT563 INVERTING - HCT573 NON INVERTING

HIGH SPEED tPD 18 ns (TYP.) AT VCC 5 V LOW POWER DISSIPATION ICC 4 A (MAX.) 25 C COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN.) VIL = 0.8V (MAX.) OUTPUT DRIVE CAPABILITY 15 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE IOL = IOH= 6 mA (MIN.) BALANCED PROPAGATION DELAYS tPLH = tPHL PIN AND FUNCTION COMPATIBLE WITH 54/74LS563/573

DESCRIPTION The M54/74HCT563 and M54HCT573 are high speed CMOS OCTAL LATCH WITH 3-STATE OUTPUTS fabricated with silicon gate C2MOS technology. These ICs achive the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. These 8 bit D-Type latches are controlled by a latch enable input (LE) and a output enable input (OE). While the LE input is held at a high level, the Q outputs will follow the data input precisely or inversely. When the LE is taken low, the Q outputs will be latched precisely or inversely at the logic level of D input data. While the OE input is at low level, PIN CONNECTION (top view)

the eight outputs will in a normal logic state (high or low logic level) and while high level the outpts will in a high impedance state. The application designer has a choise of combination of inverting and non inverting outputs. This integrated circuit has input and output characteristics that are fully compatible with 54/74 LSTTL logic families. M54/74HCT devices are designed to directly interface HSC2MOS systems with TTL and NMOS components. They are also plug in replacements for LSTTL devices giving a reduction of power consumption. All inputs are equipped with protection circuits against discharge and transient excess voltage.

PIN No SYMBOL to Q7 NAME AND FUNCTION 3 State output Enable Input (Active LOW) Data Inputs 3 State Latch Outputs

PIN No SYMBOL to Q7 NAME AND FUNCTION 3 State output Enable Input (Active LOW) Data Inputs 3 State Latch Outputs

Latch Enable Input Ground (0V) Positive Supply Voltage

X: DON'T CARE Z: HIGH IMPEDANCE Q/Q OUTPUTS ARE LATCHED AT THE TIME WHEN THE LE INPUT IS TAKEN LOW LOGIC LEVEL.


 

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